TPS3762: Sense detect time delay issue

Baris Yetkil

Part Number: TPS3762

Tool/software:

Hi,

In our latest design we used TPS3762D02OVDDFR for protection and gate monitoring.

If an over voltage condition occurs on gate control voltage equal to or more than 200us we immediately turn-off VDD of Gan Power amplifier.

According to datasheet(https://www.ti.com/lit/gpn/tps3762) if no cap is connected sense delay time is around 80-100us.

Additional 20pf is inserted for sense delay of around 150-200us.

As far as we understand from this datasheet, OV conditions shorter than 150–200 µs will be ignored. Any longer OV condition will assert RESET!.

However lab measurements tell a different story. As soon as the OV condition occurs reset is asserted.

Any help is greatly appreciated.

Note: We double checked device part number on Digikey package but no mistakes.

Is there a way to identify IC on microscope for device number in case of packaging error?

2 months ago

0 Jesse Villanueva 2 months ago

TI__Mastermind 18710 points

Hi Baris,

Would it be possible to get a schematic for this design to help with the debug process?

After the device I dentification, it should have the top marking code on the IC.

Jesse

0 Baris Yetkil 2 months ago in reply to Jesse Villanueva

Prodigy 10 points

Hi Jesse,

After posting this issue we noticed and checked IC marking under microscope. It is 62D02 which is correct according to datasheet.

Below is the schematic.

PDA_VGS is between -5V and -2V. There hold is adjusted to VGS -3.5V with R5814 and R5817.

If VGS is -2V for longer than 200us, VDD shall be turned-off immediately.

At the moment we adjust the time with C5820 since we couldn't adjust it with CTS pin cap.

Regards.

Baris.

0 Jesse Villanueva 2 months ago in reply to Baris Yetkil

TI__Mastermind 18710 points

Hi Baris,

My immediate guess is going to be the 20pF may be too small for the CTS to detect. I am checking with our design to see if there is a minimum capacitance value for the CTS pin on this device. Adjusting the C5820 may be the correct solution for this issue.

Jesse

0 Baris Yetkil 2 months ago in reply to Jesse Villanueva

Prodigy 10 points

Hi Jesse,

Before posting this issue we checked with 120pF. Also dismounted IC and mounted a new IC without any resolution.

We will check with a larger cap 1n-10n in the lab.

Baris.

0 Jesse Villanueva 2 months ago in reply to Baris Yetkil

TI__Mastermind 18710 points

Hi Baris,

Quick question, what is the status of the BIST_EN/LATCH_CLR pin during testing?

Jesse

+1 Baris Yetkil 1 month ago in reply to Jesse Villanueva

Prodigy 10 points

We we very busy with the new design. I just had time to check this in pcb.

After Latch is enabled, 20us test pulse is applied. Sense delay is around 200us.

Lacth_CLR is active low during the test pulse, and Reset! is latched for this short test signal.

Green signal(reset!), blue(BIST_EN/LATCH_CLR), yellow(sense signal at resistor divider input)

0 Jesse Villanueva 1 month ago in reply to Baris Yetkil

TI__Mastermind 18710 points

Hi Baris,

Unfortunately, the device does not allow the use of the CTS pin when latch is activated. This feature is going to be added in the datasheet in the next revision.

Jesse

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TPS3762: Sense detect time delay issue