Tool/software:
Hi,
We need to control and monitor the UCD9081 in an embedded system.
All questions below apply to the following documents:
- UCD9081 datasheet (SLVS813C - JUNE 2008 - REVISED NOVEMBER 2016)
- UCD9081 programming guide (SLVA275C - JANUARY 2010 - REVISED MAY 2023)
1. Configuration data areas (datasheet section 8.4.4, programming guide section
5.2.1) - it is my understanding that the UCD9081 contains two Flash areas:
- The user parameters section starts at address 0xE000
- The application parameters section is not directly visible to the user
The device automatically reads and writes the application parameters section as
described in the programming guide (section 5.2.1).
The user parameters section can be written and read via I2C.
UCD9081 can write the user parameters section (without user command) if its checksum
test fails, as described in the programming guide.
a) Is my above understanding correct?
b) The datasheet says that during the reset sequence the device does not communicate
on I2C. I presume that this means that it returns a NAK when accessed. How long can
this condition (the device not communicating on I2C) last after a reset?
The programming guide mentions several nominal delays (35 ms, 102 ms). Do these only
apply at power-up, or also after every RESTART command?
2. Sequence after shutdown (datasheet section 8.4.8.6):
a) If I understand correctly, when a fault occurs on a rail configured for
"retry n times" mode and the n times counter expires, the system is shut down.
When "sequence after shutdown" option is selected for an output (a rail enable or a
GPO), that output is sequenced after the shutdown. What happens to other outputs
(rail enables and GPOs) for which "sequence after shutdown" is not selected? Are
such outputs left in shutdown state following the reset after shutdown sequence?
b) The datasheet says:
"If a rail is configured for sequence after shutdown and is forced to shutdown due
to a fault on a parent rail, a sequence after shutdown takes place".
A rail (or a GPO) can be forced to shutdown because of any of the conditions listed
in datasheet section 8.4.7, namely:
- A fault condition on the rail itself (and, according to my understanding, the rail
is configured for "retry n times" mode)
- A fault condition on a parent rail (which, according to my understanding, is
configured for "retry n times" mode)
- A shutdown command from I2C.
What will happnen in each of these cases for a rail for which "sequence after
shutdown" option is set?
3. Resetting the Flash error log (datasheet section 8.5.3) - I presume that after the clear
commands are issued, the device performs the internal Flash clear operation.
a) How long does it take?
b) Does the device communicate on I2C while a Flash clear operation is in progress?
4. Writing device configuration data (datasheet section 8.5.4):
Flash programming normally involves Flash erase and Flash write. Flash erase
starts when 0xBADC is written to WDATA. According to the programming gude, while
Flash erase is in progress, the device stretches SCLK. This nominally takes 12 ms.
What about Flash write?
a) When does Flash write occur? when have received a segment, or when have received the 512th
byte (for the case of configuration data write), or when?
b) Does the device allows to communicate with it over I2C while actual Flash
programming is in progress? Or does it also perform SCLK stretching at this time?
c) If it is not possible to communicate with the device (or on the bus) during Flash
write, how long can it take for Flash write operation to complete?
d) If the device does support I2C communication while Flash write is in progress, is
it possible to know when Flash write has ended by polling bit 1 of the FLASHLOCK
register?
5. On-line fault log reading (datasheet section 8.6.3):
a) Reading an entry in the error FIFO requires reading from 6 registers. When
exactly is the ERROR FIFO advanced? When the ERROR6 register is read?
b) Error FIFO entry copmprises a timestamp. Such time stamp can represent time up to
about 256 hours. What will happen if an alarm occurs after more than 256 hours after
a restart? Is the time tag counter cyclic (i.e., will it roll through zero)?
6. STATUS register (datasheet section 8.6.4)
6.1 NVERRLOG (bit 5) - what will be the status of this bit when there are entries in
the non-volatile log and the device is --not-- held in reset?
6.2. FW error (bit 4) - the datasheet says that this error is flagged when "device
firmware memory contents are corrupted". It also says that when this error is
flagged, the device is idle.
a) What is "device firmware memory"? Is it the configuration data in Flash?
b) Is it possible to recover from this error by writing new configuration data to
Flash (as described in section 8.5.4)?
7. RAILSTATUS1 register (datasheet section 8.6.6) - I understand that RAILSTATUS2 bits
indicate error status of rails 1-8. What is RAILSTATUS1 register used for?
8. Flash error log read while the device is not held in reset (section 8.6.10) -
the datasheet says that the log can be read by performing an "I2C read transaction
starting at address 0x1000 with a length of 48 bytes".
Is it required that the read be performed via a single I2C transaction?
9. Programming guide section 4.2.14 - what is the address of the SaveRailLog
configuration data field? I suspect that it is 0xE180, however the datasheet does not
say so.
Please advise.
Thahks,
