UCC28064A: GDA and GDB output stopped

Hello Hirotsugu-san,  

Distortion of the VINAC signal itself would not stop GDx pulses. 
However, there are a few external conditions which can result in loss of GDx. 

The resolution of the screenshot is low and the graticule lines are fuzzy, but the gap in GDx pulses appear to be a little less than 1/2 of a small time division which are 1/10 of the main time division of 5ms/div.  The small divisions are 500us/div, and the gap appears to be about 200us wide on that scale. 

This suggest to me that the ZCD_A and ZCD_B signals failed to reach one of the thresholds (either 1.7V rising or 1.0V falling) to keep transition-mode switching going. 
When the ZCD signals are not sufficient to reach the thresholds, switching stops.  There is a "watchdog" timer (Tstart) within the UCC28064A that will trigger a restart pulse every 210us on each gate-drive to try to restore switching in the event of loss of ZCD. 

Since this event occurs near a zero-crossing where the input voltage is very low, I suspect that the ZCD_x voltages were unable to rise high enough during the MOSFET on-times to reach the 1.7V arming threshold, so the ZCD circuits were not enabled to trigger the next switching pulse at the end of the current switching cycle. 

Although this can be considered not an ideal situation, loss of switching at the AC zero-crossing is not necessarily a significant problem either. 
If this gap must be eliminated, redesign of the ZCD circuit may be necessary, especially changing the turns ratio for higher signal level. 

This GDx gap may also be caused by a brief output overvoltage, but since it happens near a zero-crossing, I think it is very unlikely. 

Regards,
Ulrich

Hi Hirotsugu-san,  

As I mentioned before, the distortion on VINAC is not causing the GDx outage.  However, whatever event is causing the distortion of VINAC is also the most likely cause of the GDx outage. 

Since VINAC has a flat spot at or near zero volts when the outage happens, I suspect that the AC input also has an interval of zero volts which can result in insufficient voltage for the ZCD_x inputs to continue transition-mode switching. 

Please check the AC input at these events. 

It is interesting that the VINAC stays at 0V for a much longer duration than GDx outage.  That implies that the ZCD_x signals recover to normal operating levels sooner than the VINAC signal does.  Which implies that the AC input rises above 0V sooner than the VINAC signal indicates. 
Please check that situation as well. 
Is it possible that the VINAC signal is not simply a resistor divider from the rectified AC line, but is being controlled by some other circuit with a delayed enable? 

In any case, see what is happening at the AC input first, followed by the voltage after the AC rectifier, and what the ZCD_x signals look like during this event. 
The VINAC signal distortion is a by-product of the event, but it does provide a clue for further investigation of the actual cause. 

Regards,
Ulrich 

Hi Hirotsugu-san,  

From your latest waveforms, yes, it makes sense that it is the loss of ZCDx signals that causes the GDx stopping. 

The distortion on VINAC also makes sense, due to the switching of the inrush thyristors.
VREC shows the actual switching on the voltage after the bridge rectifier, but the noise filter capacitor on VINAC filters out the switching and only the average voltage (scaled down by the resistor divider) is seen.

It is possible that there is enough variation in the ZCD threshold levels so that 5 of 7 boards see this issue, but I think not probable.  
I think there may be more variation in the thyristor switching or the inductor ZCD-winding coupling than in the ZCD thresholds.  

This waveform is of the ZCD-winding voltage itself (due to the high scale 50V/div) and you can see it fall to ~0 at the AC line crossover.   

That is where the ZCDx signals are lost and switching stops for ~210us until the internal restart-timer restarts the switching. At that point, the voltage after the bridge is lower than normal so there appears to be irregular resumption of switching. 

I think thyristors can be used with UCC28064A for inrush current prevention, but it looks like the thyristor protection is activating more often than necessary.  Once inrush is complete and the output capacitor is charged, the thyristors should be continuously on for each half cycle.   
Please check the thyristor gate-drive to see if something is causing the thyristor to toggle on/off rapidly at low voltage.  Maybe that can be prevented. 

Regards,
Ulrich

Hi Hirotsugu-san,  

Certain faults, like OCP and OVP will stop GDA and GDB at exactly the same time. 
Loss of ZCD can occur at the zero crossings and at peaks of high line if the high line voltage peak is too close to Vout, but usually the loss of ZCDA and ZCDB are not simultaneous and there may be one or few cycles between loss of GDx. 

In this case, I think medium to heavy loads are pulling Cin voltage to PGND and ZCDx is lost due to insufficient voltage across the inductor.
At light loads, Cin can retain a charge and it voltage may not reach 0V and so ZCDx can be generated and switching can continue right through the zero-crossing. 

I don't think that the switching gap at zero-crossing is a bad thing, although it may appear distasteful to some people.

The inrush thyristor (identified as SCR in a snippet, above) will shut off when its current goes to zero. 
It should be turned on again each half-cycle as Vin rises above 0V, however, I think it should stay on and not pulse dynamically for ~25% of the half-cycle. 

Since this behavior is not consistent, but skips several half-cycles (not always the same number of half-cycles), I think there may be some thermal cause for the behavior, where the latching current level becomes a little higher after it warms up a few half-cycles.  Then cools down during the half-cycle where it won't stay started and the "cycle" repeats.  Or, some phenomenon similar to what I described.

In any case, I think the distortion is an SCR parameter or SCR gate-drive issue, not a PFC control issue.    
The switching gap is due to loss of ZCDx, and it can be improved a little by increasing the value of Cin (but that adds more distortion at light loads) or by changing the ZCD-winding turns ratio on the boost inductor (but that increases the ZCD current stress at high line). 
It may not be possible to eliminate the gap under all conditions.  

If the small gap is not objectionable, it can be accepted as normal operation an no design change will be necessary. 

The sporadic SCR distortion will need some kind of design change to eliminate it. 

Regards,
Ulrich

Hi Hirotsugu-san,  

I'm sorry for my delayed reply.  I was out-of-office all of last week, and I'm now trying to catch up on open items. 

To your question from 11 days ago: Loss of ZCDx can not be definitively determined from the waveforms of VINAC, IAC, GDA and GDB alone. 
They provide strong evidence to support loss of ZCDx, but not definite proof. 
For that, you must directly examine the ZCDx signals themselves. 

During the MOSFET on-times, the ZCDx signals should be < 1V.  During the MOSFET off-time, while the inductor current is discharging into the output capacitor, ZCDx voltage should be > 1.7V.   When the inductor current falls to zero, the voltage across the inductor also falls at a rate limited by the switched-node capacitance.   

At very low voltages near the AC zero-crossing, the UCC28064A extends the MOSFET on-time in order to build up enough inductor current to charge up the switched-node capacitance up to Vout and deliver some energy to the output.  During the on-time, the voltage at ZCDx should be clamped to ~0V. But with input so low, the voltage across the inductor during turn-off will be very high, so turn-off time is very short.  There may not be enough time for the off-time voltage to rise above 1.7V to arm the controller to look for the next ZCD falling edge below 1V.  

If the controller is not armed, the next pulse will not happen, and switching on that phase stops (until the internal starter timer restarts it).
Both phases are subject to the same conditions, but they may not respond exactly the same due to small variations in thresholds and parameters.

Decreasing the turns ratio will apply a higher ZCD voltage to the R-C network on ZCDx during the MOSFET off-time, and this may overcome the loss of ZCDx at the zero-crossing, but it will also increase the current stress into the pins.      
Increasing the series ZCD resistors will mitigate that, but the ZCD caps must be reduced to restore the time constant. 
On the other hand, a lower turns-ratio will also reduce the voltage across the inductor during the on-time, and that lower voltage at the zero-crossing may not pull enough current out of the ZCDx cap to drive its voltage < 1V if the on-time is suddenly shorted by  some transient condition.  In this case, switching will also (temporarily) stop.  

You can try reducing and increasing turns ratio to see what happens. 
Loss of ZCDx may happen under various repeatable or transient conditions, and the internal starter timer will restart switching.  
In my opinion, I'd prefer to lose switching at the zero crossings where virtually no current is flowing anyway, than to lose it at the peak of high line. 

Regards,
Ulrich