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LM25143: Hiccup Mode Current Limiting (RES) triggered when Vin above certain level

Part Number: LM25143
Other Parts Discussed in Thread: INA226

Tool/software:

Hi Ti expert,

I am using LM25143 to convert a 12~24V into 0.88V, Iout 60A to power a Xilinx SoC.
but now I seeing Hiccup Mode Current Limiting (RES) triggered, Vout halt for ~10ms, when under operation
I connected my testing board to DC load, seeing this symptom is affected by Vin level, higher Vin more easy to triggered.

is there anything I can optimize my design ?

Thanks,
Alex

LM(2)5143-Q1 quickstart design tool - 0p88V_60A_design 1%.xlsm

  • Hi Alex,

    If you increase the inductance to around 2uH per phase does that fix your design? Can you share p/n of Inductor you are using?

    Thanks,

    Andrew

  • Hi Andrew,

    Thanks for replying.

    It would be quite challenging to replace inductor... due to my board size...

    1/ Current Inductor P/N "IHLP5050FDERR10M01"

    2/ I would like to ask what is the worst case scenario if I short pin "RES" to "VDDA" to disable Hiccup-mode protection?

    3/ And I found below description in datasheet...
    Do I need to change the Fsw as well?

    Thanks

  • Hi Alex,

    Yeah 0.8V/24V is a steep conversion ratio. It seems like the issue you are running into is the min_Ton of the device. Yeah you may need to lower the FSW 10-20KHz the value that Eq 8 gives you. However, this will necessitate a higher COUT and L requirement, especially if the Xilinx device has a strict ripple requirement.

    Thanks,

    Andrew

  • Hi Andrew,

    Due to equipment limitation, I can only change the Cap and Res value on my board.

    In my 1st try, I had tune down the Fsw to 560kHz and change to compasation circuit to corresponding value (detail value in attached table) 
    after plug to DC load, I can see some improvment that I can draw more current before trigger the Hipcup.

    any Idea which part I should change?

    Thanks.

    LM(2)5143-Q1 quickstart design tool - 0p88V_60A_design 1 - 560kHz.xlsm

  • Hi Alex,

    It may be possible just by lowering FSW and raising C and changing comp values.

    I took a look at the new excel. My feedback is that you can lower the desired crossover frequency too (rule of thumb is set it to 1/10FSW).

    Thanks,

    Andrew

  • Hi Andrew,

    Thanks for the advise.
    I had done a quick compare of the comp value change, detail in below table
    but the result are not positive.

    I may think of increase the inductor value in my next sample.

  • Hi Alex,

    Let me check with the team.

    My instinct is to increase L -> 0.2uH. I know you don't have access to a solder rework station, but that may be the solution. I also think you need an even lower switching frequency in order to work at the higher input voltages. @VIN = 28V you need FSW < ~439KHz.

    Thanks,

    Andrew

  • Hi Alex,

    Can you send the scheamtic? I'm curious how the Isense circuit is set up. Engineer for the part suggests using 2mOhm to set the current limit.

    Thanks,

    Andrew

  • Hi Andrew,

    you are right about I should cover the Vin max corner case.
    I will also consider the change.

    Please find me before and after schematic in below
    Beside the 470uF Cout show in below, there are more MLCC near the FPGA input.

    Before:
    Inductor P/N: IHLP5050FDERR10M01
    Shunt res P/N: CSRL3-0R002F8
    Cout Cap P/N: T598D477M2R5ATE009

    After change to Fsw=560kHz:
    I also change the Shunt res to 5W part.
    Revised VCCINT sch.pdf

    Thanks,
    Alex

  • Hi Alex,

    Thanks for sending the schematic.

    The current sense capacitor (C62) seems quite large. I normally see something on the order of a 10's of pF, but the design shows 100nF.

    It acts as a low pass filter in applications. Mainly customers tune RC to be equal to L/R of the shunt resistor.

    Let me know if playing around with this solves the issue.

    Thanks,

    Andrew

  • Hi Andrew,

    Sorry for late reply. Finally I have some time return to this case.
    the cap C62 low pass filter is for the current sense chip "INA226", so it is stay away from "LM25143" and will not affect on the circuit.

    And I had probed the SW waveform at min / max DC load before IC trigger the protection
    which give a interest finding that SW duty cycle is reaching calculated max value

    Condition:
    Vin = 12V
    Vout = 0.88V
    fsw = 560kHz (1.78us)

    so the max duty cycle = 1.78us * (0.88/12) = 130ns
    but below probing on SW found duty cycle is around 140ns
    do these giving any hints I should change which part?

    SW at min DC load

    SW at max DC load before trigger protection

    Thanks,
    Alex

  • p.s. min DC load means drawing 1A
    Max DC load means drawing ~22.5A, which is far from design target

    p.s. my setup is not prefect that soldering is involved to connect to DC load.

  • Hi Alex,

    The capacitor will still affect the circuit. Please have them check the circuit if they remove it, or change it to 10pF.

    Sorry for late reply. Finally I have some time return to this case.
    the cap C62 low pass filter is for the current sense chip "INA226", so it is stay away from "LM25143" and will not affect on the circuit.

    Thanks,

    Andrew

  • Hi Andrew,

    I just change it to C62 to 10pF, but still the circuit shut down way below design target.

    Vin = 16V, Iout before shut down = 9.8A

    Thanks,
    Alex.

  • Hi Alex,

    Do you have any way of measuring the inductor current? Can you share that? I'm wondering how much current the device is pushing when it shuts down.

    Thanks,
    Andrew