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UCC21750-Q1: I want to know about the UCC21750 Desat function settings and operation method

Junehee Park
Intellectual 320 points
Part Number: UCC21750-Q1

Tool/software:

Hi~

I have a few questions.

1. When I designed and measured the Desat circuit as shown below, it worked as shown in the measured waveform. Please check if it is working normally.

2. If the desat setting value is 7.52V, how does desat work? If it gets bigger than the fixed value of 9V, does desat work, and if it gets smaller, does desat not work?

3. When the Gate turns On and Off, a peak noise occurs in the Deset waveform. Why does this occur?

4. What is the range of CBLK values ​​for the desat circuit?

  • 0
    TI__Mastermind 22806 points

    Hi Junehee,

    1. It looks like your DESAT pin is charging up to a fixed value every time OUT goes high, which is expected in normal operation. In a desaturation event, the DESAT pin voltage will charge all the way up to 9V, and then the output will turn off, even though the input is still high. Then, nFLT will pull low and latch.

    2. Vdesat_actual means that when the Vce reaches 7.5, the voltage at the DESAT pin will charge to its 9V threshold, due to the desat diode drop and the series resistor drop. Thus, the circuit effectively is detecting if Vce is above 7.5V, not 9V.

    3. There is usually noise injected into the DESAT capacitor when the output switches. This is simply due to parasitic coupling and the proximity of the pins. It is most important to suppress this noise injection on the OUT rising edge, as this can corrupt the DESAT timing. Therefore, there is a leading edge blanking time, where the noise is shunted by a closed switch (t_DESAT LEB). The DESAT should not trigger on the falling edge, since the output is already OFF.

    4. The capacitor can be as large as you want, but the IGBT will be damaged if DESAT does not trigger fast enough. On the other hand, you can usually use a capacitor as low as 50pF. But lower than that creates a noise immunity issue. That is, noise injection starts to change the DESAT voltage. One way to decrease the DESAT time without decreasing this capacitor value is to use an external resistor from VDD to DESAT. This adds charging current, and allows you to use a more noise tolerant larger capacitor.  

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Intellectual 320 points

    How can I eliminate the noise in item 3?

    How and how much value should I connect the external resistor from VDD to DESAT in item 4?

  • 0 in reply to Junehee Park
    TI__Mastermind 22806 points

    Hi Junehee,

    The DESAT current is 500uA by default. If you wanted to double you capacitor size and maintain the same DESAT trigger delay, you would need to add another 500uA. If you have 15V from VDD-COM, a good resistor to use is 15V/0.5mA= 30k Ohms.

    You can't really eliminate the noise injection externally, other than integrating it down with a larger capacitor, but the leading edge blanking time is designed to internally shunt the noise. The noise should not matter on the falling edge, since DESAT is already being deactivated during the falling edge.

    Best regards,

    Sean