UCC21330-Q1: UCC21330とAMC1311BQDWVRQ1

Hi Hebishima-san,

Thank you for your interest in our devices.

The insulation specifications found under 5.6 Insulation Specifications in the product's datasheet will be the right reference to use when analyzing the insulation.

As long as these specifications along with other ratings and recommendations in the datasheet such as the layout are followed, there should not be a risk for breakdown of the insulation barrier.

If there are any specific questions regarding these, please feel free to let me know.

In regards to the AMC1311BQDWVRQ1 part, please post a separate thread with this device tagged to receive support from the dedicated expert for this device.

Thank you!

Regards,

Hiroki

Dear TI Support Team,

Thank you for your continued support.

We have confirmed from the datasheet that the device is specified as providing basic insulation. However, we were unable to determine from the datasheet whether the internal insulation barrier of this driver is constructed as double-layered or not. Could you please clarify this point?

Additionally, we are concerned about potential failures caused by PCB layout around the IC and mechanical stress on the board, which are not explicitly described in the datasheet.
Could you advise on what kinds of failure mechanisms or design considerations should be taken into account in these areas?

We appreciate your guidance and look forward to your response.

Best regards,

Hi Hebishima-san,

Happy to help! Thank you for following up.

I can confirm that UCC21330-Q1 has single level insulation that provides protection against shock.

szzm003a (4).zip

The attached zip file will contain an application guide which includes PCB layout design considerations and guidelines.

Please let me know if you have additional questions!

Regards,

Hiroki

Dear Mr. Hiroki Honda,

Thank you very much for your response. I now understand that the UCC21330-Q1 provides single-level insulation.

In my application, insulation breakdown would constitute a hazardous event, so it is essential to clearly indicate the countermeasures implemented to prevent such occurrences.

To that end, I would like to ask for some additional clarification:

1. I understand that adhering to the specifications in the datasheet is key to preventing insulation breakdown. However, I would like to confirm which factors are particularly influential in causing such failures.

   I believe that voltage stress and ESD applied to the input and output pins are relevant concerns. Would you agree with this assessment?

2. Alternatively, is the most critical factor the application of overvoltage between the isolated pins?

I appreciate your guidance and look forward to your response.

Best regards,
Koki

Hi Hebishima-san,

Happy to help.

Thank you for sharing the helpful details here.

Addressing your questions:

KOKI HEBISHIMA said:

I understand that adhering to the specifications in the datasheet is key to preventing insulation breakdown. However, I would like to confirm which factors are particularly influential in causing such failures.

Outside of the datasheet specifications, the most important factor for preventing insulation breakdown would be the layout. However, designing around the layout recommendations will help prevent this from occurring. Recommendations such as avoiding traces/routing below the device, maintaining creepage between the primary and secondary sides as well as between channel A and channel B, will help.

KOKI HEBISHIMA said:

• I believe that voltage stress and ESD applied to the input and output pins are relevant concerns. Would you agree with this assessment?

• Alternatively, is the most critical factor the application of overvoltage between the isolated pins?

I agree with your statement, however these should be characterized under the following datasheet sections:

• 5.2 ESD Ratings for ESD related stress
• 5.6 Insulation Specifications for voltage stress

Please let me know if you have specific questions about these specifications.

Regards,

Hiroki