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TPS65131-Q1: Design review, large output and input ripple at light loads

Samuel Eriksson
Prodigy 20 points
Part Number: TPS65131-Q1
Other Parts Discussed in Thread: TPS65131EVM-839, TIDA-00689, TPS65131,

Tool/software:

Hi TI Expert!
We have implemented a 5V to +/-15 supply in one of our designs. The load is light, below 20mA but hopefully below 10mA.
The following information was used as a foundation for the design, i.e. component selection and layout: datasheet typical application (4.7uH), eval. board design TIDA-00689 (this is our main reference, we also need a compact design, 10uH), eval. board design TPS65131EVM-839 (for TPS65131, 4.7uH)
L1, L3 is Wurth 744031006 (6.8uH). It is a compromize between 4.7uH and 10uH in an attempt to minimize ripple. The inductor family Wurth 744031XXX is recommended in the datasheet.
Our issue is the large output ripple at light loads (i.e. no load, 3mA or 10mA) when enabling the power save mode (PSP, PSN high). Efficiency and low ripple is prioritized because the power supply will be used in a battery powered sensor system.
Especially the +15V ripple is too high (>150mV p-p, not uniform, see below) and it also generates a 200 mV p-p ripple at the 5V input supply even when supplied from a linear lab supply.
Figure 8-11 in the datasheet shows a 50mV pp VPOS ripple with power save mode on and 20mA load.
The general VPOS ripple in our measurement is similar but sometimes TPS65131-Q1 seems skipping controlling the output voltage for some time which generates a larger p-p ripple. Also the voltage increases suddenly, this doesn't align with Figure 8-11. With power-save mode OFF, the ripple looks more normal, see below.
The 5V supply is generated by an isolated DC/DC converter in the complete design. The large current ripple at the input of the TPS65131-Q1 circuit interferes with the isolated DC/DC output voltage control which is another issue.
Schematic diagram:

+15V ripple at 3mA load, power-save mode ON (discard ch2)

+15V ripple at 8mA load, power-save mode ON (discard ch2)

+5V ripple, power-save mode ON (discard ch2)

+15V ripple at 10mA (?) load, power-save mode OFF (discard ch2)

+5V ripple, power-save mode OFF (discard ch2)

  • 0
    TI__Mastermind 34840 points

    Hi Samuel,

    Large voltage ripple when power save mode enabled is as expected, you can try decreasing the inductance to maybe 4.7uH to see if there is any improvement.

    BR

    Patrick

  • 0 in reply to Patrick Yao
    Prodigy 20 points

    Hi Patrick,

    Thanks for your answer.
    I took me a while to reply to your post because I was troubleshooting something which influenced power consumption. The measurements below are more representative of our implementation.

    With power-save mode turned off, TPS65131 power efficiency in our application is 18-28%, see below. Since +5V_ISO is supplied from an isolated DC/DC, this will make overall power efficiency very low. This system is battery supplied in many applications, so power efficiency is important. The current external supply supplying this system is also limited to 600mA. Therefore, we would like to get the power-save mode to work if possible. A major reason why this IC was selected was because the overall solution of eval. board TIDA-00689 matched our design goals well. In the TIDA-00689 design, power-save mode was used.

    You say that the ripple we have measured is expected. If we can accept the output ripple amplitude of +15V and -15V, there are some other things we didn't expect:
    1. The irregular +15V ripple control. General ripple is about 50mV which is fine but sometimes it is >100mV. We expect ripple to be controlled evenly. Now it looks like the control loop skips controlling the output from time to time. Do you have an explanation and solution for this? Could this be improved with 4.7uH coils? Could the voltage ripple amplitude be in the same range as system noise floor?
    2. Is the fast +15V rising edge expected? Fast rising edges gives much EMI. Is doesn't match measurements in the datasheet but could the light load be an explanation?
    3. The input +5V_ISO ripple is unacceptable (200-300mVp-p), this is our biggest concern. In this test +5V_ISO was supplied from a linear lab supply. The implemented isolated DC/DC not surprisingly control the output voltage worse than the external linear lab supply. The peak ripple current has been measured to more than double the average current (ch2, note that time scale is 50us/div):

    Obviously we want the ripple to be handled internally as much as possible within the TPS65131 circuit.
    Do you have an explanation or solution for this? Note again that we have tried to follow the TIDA-00689 design.

    PSP, PSN high (power-save mode turned on)
    Minimum +/-15V load: quiescent current supplied circuits
    I(+15V) = 3.3mA
    I(-15V) = 2.9mA
    I(+5V_ISO) = 47mA
    Efficiency: 38%
    Maximum load: 1mA RMS sine wave
    I(+15V) = 6.6mA
    I(-15V) = 4.9mA
    I(+5V_ISO) = 69mA
    Efficiency: 49%

    PSP, PSN low (power-save mode turned off)
    Minimum +/-15V load: quiescent current supplied circuits
    I(+15V) = 3.3mA
    I(-15V) = 2.9mA
    I(+5V_ISO) = 101mA
    Efficiency: 18%
    Maximum load: 1mA RMS sine wave
    I(+15V) = 6.6mA
    I(-15V) = 4.9mA
    I(+5V_ISO) = 120mA
    Efficiency: 28%

  • 0 in reply to Samuel Eriksson
    TI__Mastermind 34840 points

    Hi Samuel,

    Smaller inductance will reduce the energy provided to the output caps in light load, so theoretically it will help to improve the output ripple.

    For the +5V_ISO ripple, is it measured with power save mode on or off? Larger input capacitance may help to reduce the ripple.

    You can also try increasing the external power supply current limit to avoid the inrush current reaches to this limit and cause additional voltage drop.

    BR

    Patrick