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UCC15240-Q1: Connect PG pins together

Vivek Gandham
Intellectual 260 points
Part Number: UCC15240-Q1

Tool/software:

Hi Team,

I am planning to use UCC15240/UCC15241 in inverter application. I have the following question mentioned below

1. Can we tie all the PG pins together to get the status of all Gate Drivers?

2. Can we use this IC with output 5V? Is this recommended?

3. Do we need any dummy load on the output side of UCC15240/1? if needed how much do we need?

Regards

Vivek  

  • 0
    TI__Mastermind 33045 points

    1. Can we tie all the PG pins together to get the status of all Gate Drivers?

    • Yes but be aware that when a /PG fault is read, you will not know which device(s) has experienced the fault

    2. Can we use this IC with output 5V? Is this recommended?

    • No, UCC15240 output cannot regulate down to 5V

    3. Do we need any dummy load on the output side of UCC15240/1? if needed how much do we need?

    • No, UCC15340 can regulate down to no load

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Intellectual 260 points

    Hi,

    Can confirm how much it can be generate minimum?

    Regrads

    Vivek

  • 0 in reply to Steven Mappus1
    Intellectual 260 points

    Thanks for the information,

    i am also planning to use with 15V as output, as mentioned in above picture minimum operating voltage is 15V, to operate at this voltage should i need to consider any other parameters like addition cout caps for having minimum regulation? and there is also UVLO on secondary side for this IC, is there any chance to go UVLO protection with 15V output? What is the behaviour of IC, if it goes to less than 15V like 14 or 13V?

    And for single output circuit, if we are not using Rlimit resistor (connect to Vdd, as mentioned optional ), can we keep the Rlim PIN  open?

    Regards

    Vivek

  • 0 in reply to Vivek Gandham
    TI__Mastermind 33045 points

    UCC15240 will regulate to VDD-VEE=15V. there is output UVLO protection and this is monitored by the FBVxx pins dropping below 2.25V. If output UVLO fault protection is triggered, the UCC15240 will latch off (stop switching, no output) and you would need to toggle EN or VIN to clear the fault and initiate a new sift start cycle. 

    For single output configuration connect FBVDD=FBVEE=short together, make a single feedback resistor divider from VDD-VEE and you can leave RLIM as open.

    Steve