Tool/software:
Hello,
It is very obvious that grounding is a big emphasis on the data sheet.
1)When putting in thermistors into the GPIO pins, It seems that the power comes from TSREF, which has a bypass grounded to CVSS. Since the GPIO is read by the internal ADC, is each GPIO Grounded to AVSS or CVSS. It seems that in the EVM layout that the GPIO is referenced to AVSS. If AVSS is the ground, why would TSREF be bypassed to CVSS?
2)Since all cell readings are taken from the internal ADC, would negative side of cell1 be the AVSS reference? In other words, Figure 10-1 (P190) Would the SRN pin be connected to AVSS?
3)When tying all grounds together on L3 as shown in 12-6 (P207), is it recommended to have many stitching vias or only a few on each individual ground to minimize noise coupling?
4)When tying these grounds together is it recommended to use a Y type capacitor between the grounds? Why or Why not?
Thank you