Part Number: LP5024
Tool/software:
Hi Folks,
A couple of questions regarding the I2C timing specs for the LP5024:
- Is the rise and fall time specs for SDA and SCL referenced to 30%/70% voltage levels as per the I2C spec, or is this referenced to different voltage levels (20%/80%, 10%/90%, etc.)?
- Would there be any concerns with a fall time that is <15ns? The host on the I2C bus has a relatively strong driver producing fast edge-rates
Thanks,