Tool/software:
As per the description of Section 7.4.3 & Figure 29, it is observed that VDDQ will start ramping up after some delay T2. 
If below sequence is followed will VDDQ output will be maintained low by the regulator & will be ramped up only after VPP output attains steady state? or VDDQ will attain steady state before VPP starts ramping up?
Seq #1: Supply provided to PVIN pin
Seq #2: SLP_S4 is enabled
Seq #3: Supply provided(after 50 ms delay from Seq #2) to PVIN_VPP pin