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Original question:

BQ40Z80: DSG FET burning up

BQ40Z80: Alternative for CSD1854Q5B

OverAgent712
Intellectual 470 points
Part Number: BQ40Z80
Other Parts Discussed in Thread: CSD18536KTT, CSD18540Q5B

Tool/software:

Hello,

Despite the CSD1854Q5B suggested to use with BQ40z80, it has 29A discharge current. Wanted to have 60A discharge current MOSFET, currently with 29A, 3 are being used, but there is heating once it crosses 40 A like 85 degrees. So choosing a MOSFET with higher current ratings would reduce the heating i think. Is this approach correct ?
Would like some suggestions for it, Let the Package be D2PAK preferred. 
Thanks 

  • 0
    TI__Mastermind 26495 points

    Hello,

    Although your logic for putting three fets in parallel to get a higher discharge rate does appear to be logical, the biggest reason for the heat being created could be due to the Rds of the Fet being too high, not enough copper trace pour within your material and not having a efficient matter for dispensing the heat such as a heatsink or fan within your system. I will be pushing this trend to a FET team within TI and hopefully they can give you more insight as to how to better dissipate your heat issue.

    Thank you,
    Alan

  • 0 in reply to Alan Frias
    Intellectual 470 points

    Hello,
    Sure that would be helpful. And yes, we don't have any heatsink or fan within the system. The copper pour is of 19 mm width and 12 mm length uniform across all 4 layers with 2 oz copper in each layer. According to calculation this should handle around 60A I believe. The pour is filled with thermal vias. Can share the layout image in private if needed.

  • 0 in reply to OverAgent712
    TI__Mastermind 38270 points

    Hello,

    Thanks for your interest in TI FETs. Our lowest on resistance 60V FET in D2PAK is the CSD18536KTT. It is 1.6mΩ max at VGS = 10V. This appears to be a static switch (on or off) and is not switching at high frequency. The only power loss is due to I² x Rds(on). The calculated conduction loss at TJ = 55°C & ID = 60A is 6.8W which exceeds the capability (~4W max) of the package. You will probably need to parallel at least 2 FETs. This will reduce the conduction loss per FET to 1.7W.

    I also calculated the conduction loss for the CSD18540Q5B with 3 FETs in parallel under the same conditions and it is about 1W per FET assuming they share current equally. Please share your layout in private message.

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    Intellectual 470 points

    Hello, 
    Yes as per calculation there is 1W if the three are sharing same load, we looked into the thermal profile during drain test, the load share isn't equal among the three.
    I have shared the layout in provate message.

  • 0 in reply to OverAgent712
    TI__Mastermind 38270 points

    Hi,

    I have the file and I'm installing KiCad EDA to view the board layout. Unfortunately, it is taking a very long time for it to install. I will review the PCB layout and update you when I can.

    Thanks,

    John

  • 0 in reply to John Wallace1
    Intellectual 470 points

    Hello,

    Sure, thanks for the update. Will be awaiting your response.

  • 0 in reply to OverAgent712
    TI__Mastermind 38270 points

    Hi,

    Installing KiCad took several hours and it finally completed last evening. I will take a look at the layout today. In general, FETs share current naturally due to the positive temperature coefficient of Rds(on). However, it's more of a thermal current sharing and the current may be unbalanced due to differences in the FET temperatures. I'm including a link below to an app note on paralleling FETs.

    https://www.ti.com/lit/pdf/slpa020

    Thanks,

    John

  • 0 in reply to John Wallace1
    TI__Mastermind 38270 points

    Hi Manas,

    Since we have moved this discussion to private messages, I am going to close this thread. Please feel free to message me if you have additional questions.

    Thanks,

    John