Tool/software:
Hi,
we are using multiple TPSM82913 modules in our new device design, some of the converters are synchronised to power domain spread spectrum reference clock. Hovewer, we have discovered intermittent failures of the module to enable despite the operating conditions being within valid range.
On some sample boards, we noticed intermittent failures of power-on sequence that usually can be recovered by power cycling the board. After further investigation, it turns out that the modules are not enabling with valid clock signal present on their enable pin. When such failure occurs, NR/SS pin is stuck at 0V, no soft start ramp is generated. Recovery is usually possible by holding the enable pin low
For testing purposes, we repeated the same with disabled frequency modulation with fixed tone at 1MHz - the result is same, intermittent failure to enable the module.
It is possible to trip the failure not just by gating the enable clock signal, but also at random during first enable after power-on.
There is no difference in instance where output is fully isolated from the rest of our design, the intermittent failure still occurs.
Free running converter clock is confirmed to be 1MHz.
SCONF resistor is confirmed to be within +-1% value fromm 52k3.
Design parameters:
Input voltage 12V +-5%
Output voltage 3,3V
Operating frequency: 1MHz, output discharge enabled, ext synchronisation enabled.
Softstart time ~20ms.
Our integration schematic snippet:
+12V rail has bulk decouping included as well. FTH capacitor at input was confirmed to not cause any resonance with step load nor during startup, voltage droop due to DCR is less than 100mV.
Please advise.
