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TPS6594-Q1: Help debugging TPS6594-Q1

Alex Novickis
Prodigy 131 points
Part Number: TPS6594-Q1

Tool/software:

Using TPS6594133ARWERQ1, for jacinto board

PMIC has input voltage and enable event/level

However no output voltages are seen,
EN_DRV is low lighting the fail safe LED

GPIO9 can be forced low or high, with no change.

No oscillation seen on OSC32


1 Floating AMUXOUT
2 1.80V LDO_INT
3 1.80V LDO_RTC
4 3.30V VCCA
5 0V GND
6 0V GND
7 0V LDO4
8 3.30V PVIN_LDO4
9 0V LDO3
10 3.29V PVIN_LDO3
11 735mV LDO2
12 3.30V PVIN_LDO12
13 0V LDO1
14 0V nINT
15 0V SW_B2
16 0V SW_B2
17 3.30V PVIN_B2
18 0V GPIO7
19 3.30V GPIO9
20 0V nPWRON
21 0V FB_B2
22 0V FB_B1
23 0V GPIO5
24 0V GPIO6
25 0V nRSTOUT
26 3.30V PVIN_B1
27 0V SW_B1
28 0V SW_B1
29 0V EN_DRV
30 3.30V SDA
31 3.30V SCL
32 734mV GPIO1
33 734mV GPIO2
34 0V SW_B5
35 3.30V PVIN_B5
36 0V VBACKUP
37 0V FB_B5
38 0V O32_I
39 0V O32_O
40 1.80V O32CAP
41 0V GPIO8
42 40mV GPIO10
43 0V SW_B3
44 0V SW_B3
45 3.30V PVIN_B3
46 0V GPIO3
47 0V GPIO4
48 3.30V VIO_IN
49 8mV FB_B3
50 59mV FB_B4
51 3.30V VSYS_SENSE
52 8.89V OVPGDRV
53 0V GPIO11
54 3.30V PVIN_B4
55 50mV SW_B4
56 50mV SW_B4


My questions are,

1/ does this p/n come with a factory pre-programmed configuration ?

2/ Does this pre-programmed configuration have some documentation as to the expected behavior  ?

3/ Are the LDO's expected to be off ?

4/ Is the OSC32 expected to be off in this config ?

5/ Forcing a 0 or 1, into GPIO9  assuming it is a watchdog disable function,
Applying a 0, or 1 onto nPWRON/ENABLE (which is it for the pre-programmed config ?)

does not alter no power output


6/ Any ideas on debug


I ordered a launchpad 432 and EVM for this part so I can play with one out of circuit, and attach in circuit
but any insight appreciated.

On the other hand, If I assume this part is not factory pre-programmed, things make a bit more sense. However,  then, 
Can I get the setup as used in the EVK p/n as mentioned in the schematic clip







Schematic is similar to the eval kit for jacinto




  • +1
    TI__Mastermind 20237 points

    Hello Alex,

    Alex Novickis said:

    1/ does this p/n come with a factory pre-programmed configuration ?

    2/ Does this pre-programmed configuration have some documentation as to the expected behavior  ?

    3/ Are the LDO's expected to be off ?

    4/ Is the OSC32 expected to be off in this config ?

    5/ Forcing a 0 or 1, into GPIO9  assuming it is a watchdog disable function,
    Applying a 0, or 1 onto nPWRON/ENABLE (which is it for the pre-programmed config ?)

    does not alter no power output


    6/ Any ideas on debug

    1) This part is already preprogrammed from the factory. The generic part number is TPS6594-Q1, the TPS6594133A is the preprogrammed part.

    2) Yes, please see the User's Guide here

    3) Depends on the state of the PMIC/System, in the ACTIVE region, no.

    4) OSC32 needs to be active by a software command (an I2C write to a register), see the bit field below to look up in the datasheet:

    5) Forcing a level high (on the pin up to 3V3) after power is applied to VCCA, but before EN is signal is sent from low to high will disable the WDOG by default. Now this will also bypass the ENABLE signal from GPIO9 to the load switch for the IO. Hence why it is recommend that software disable the WD as this feature is only intended for DEBUG boards to aid in the disable of the WD when no MCU is present for power evaluation.

    If the glue logic between the preregulator feeding 3V3 to the PMIC is working to send the signal from low to high, the device will attempt to power up and will if nothing goes wrong there.

    6) My first thing to look at would be the voltage on LDO2, I see this to be the first issue upon bring up since the RV_SEL is enabled and if there is residual voltage (there's a section on it in the datasheet), then upon start up this would prevent a successful boot up. 

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Prodigy 131 points

    Thank you for your insight into this, some of these things are not obvious.
    Adding a load to reduce the prebias on LDO2, does indeed allow the PMIC to continue in the power sequence, but it faults a bit later now - although I see some of the voltages come up briefly.

    Since the LDO2 load goes to 120+ nodes it is a bit hard to isolate which is prebiasing before turn on, so to mitigate that long path of exploration an additional load was added on LDO2 to co-erce the LDO2 below 120mV and allow PMIC to proceed to the next step.

    I'll inspect the datasheet to see what the turn sequence is to see if I can deduce the next faulting area