Tool/software:
In Section 7.3.2 of the datasheet, a 100kΩ resistor (R1) is recommended in series between the PU pin and the gate of the external FET to control gate voltage ramp and limit inrush current for capacitive loads.
Since the FLT_GD pin is intended to indicate faults such as gate oxide breakdown — and it does so by checking whether the gate voltage reaches V(G_GOOD) ≈ 7.5V — I’d like to clarify:
Does the FLT_GD detection logic monitor the voltage directly at the PU pin (PU–SRC), or does it monitor the gate node after the R1 resistor?
This distinction is important because if a gate short occurs after R1, PU–SRC might still appear valid even though the gate is stuck, potentially suppressing a genuine fault indication.
Can you confirm how the FLT_GD logic senses gate voltage and whether the 100kΩ R1 affects its ability to detect a gate oxide short? Having a large resistor in series with the voltage sensing circuit affects the ability to determine a short, doesn't it?
Thank you!
