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LM5008A: Vsw Jitter

Sky Hsieh
Prodigy 40 points
Part Number: LM5008A
Other Parts Discussed in Thread: DRV8353RH-EVM, LM5008

Tool/software:

Hi TI,

I follow the components to design LM5008A in DRV8352RH-EVM.

When input is 36~48V and output is 12V / 350mA, the Vsw is unstable and jittering as below.

Please help to solve this situation.

  • 0
    TI__Genius 9700 points

    Hi,

    Can you capture the voltage at FB node along with the SW node waveform you sent?

    Regards,

    Niranjan

  • 0 in reply to Niranjan Nair
    Prodigy 40 points

    Hi Niranjan,

    I found the LM5008A in DRV8353RH-EVM has the same problem, I will use WEBENCH to redesign it.

    Thanks for your help.

  • 0 in reply to Sky Hsieh
    Prodigy 40 points

    Hi Niranjan,

    I use WEBENCH to design LM5008A and modify component according to the result.

    WEBENCH Design-85Vin, 12Vout, 0.35A.pdf

    The double / triple pules situation still exist.

    I also modify some components as below, but it does not work.

    1. Increase Rseries from 0.43R to 1R~2R7.

    2. Increase Cout from 10uF to 20uF.

    3. Remove Cff.

    Please help to provide some tips.

  • 0 in reply to Sky Hsieh
    TI__Genius 9700 points

    Hi Sky,

    The double pulsing typically happens when the ripple injection at FB node is too small. There are two components for ripple at VOUT and FB node. One component in phase with the inductor current (due to the series resistance) and one component out of phase with it (due to output capacitance). For switching to be uniform the component in phase with inductor current must dominate over the other.

    Have you tried all the modifications you mentioned together? 1. and 2. are in the right direction, this will allow the ripple in phase with inductor current to dominate. However removing Cff will lead to the ripple generated at VOUT being attenuated by the feedback resistors before reaching FB. Can you try just increasing the Rseries and Cout while still having Cff?

    Regards,

    Niranjan

  • 0 in reply to Niranjan Nair
    Prodigy 40 points

    Hi Niranjan,

    I found the WEBENCH design is ok, the problem is I have a 10uF for DRV8353RH IC.

    The frequency and waveform are normal after I disconnect the trace to C5.

    Is there any solution? The same problem happens on DRV8353RH-EVM.

  • +1 in reply to Sky Hsieh
    TI__Genius 9700 points

    Hi Sky,

    When you have capacitors in parallel it would be the effective resistance and capacitance that would matter. Here, the effective resistance is reduced because the 430 mOhm you added is in parallel with other paths which have very low series resistance. 

    If the C5 and C6 capacitors are mandatory, you will have to use type 3 ripple injection circuit. The implementation is given in section 8.2.2.3 b of the LM5008A datasheet.

    There is another option, that is to move the series resistance before VOUT, thereby making sure it is in series with all the capacitors. However you will need to set VOUT a bit higher to compensate for the drop across this and will reduce efficiency and load regulation. This implementation is given in section 8.2.2.3 c of the LM5008 datasheet

    Regards,

    Niranjan

  • 0 in reply to Niranjan Nair
    Prodigy 40 points

    Hi Niranjan,

    I use type 3 and double pulse problem has been solved.

    Thanks for your help.