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TPS7A02: Ti-pspice model

Nathan Carter
Prodigy 10 points
Part Number: TPS7A02

Tool/software:

Is it possible to get an encrypted model for the TPS7A0215PDBVR or is there a similar device that already has a silicon accurate model for simulation?

Thanks,

Nathan

  • 0
    TI__Genius 12240 points

    Hi Nathan,

    Unfortunately we aren't able to provide a transistor-level model for the TPS7A0215P.

    Best Regards,

    Alex Davis

  • 0 in reply to Alex Davis
    Prodigy 10 points

    I have a 3.3V battery with a 1k in series with it driving a tps7a02 1.5V version with a 4.7uF bypass capacitor on both sides. There is no load at this time. The resistor is to limit the discharge current to about 1mA or so. The tps7a02 appears to be drawing 1mA again with no load. Do you see any problem with this limiting resistor as long as the part is bypassed on its input with 4.7uF?

    Thanks.

  • 0 in reply to Nathan Carter
    TI__Genius 12240 points

    Hi Nathan,

    As long as the 4.7µF input capacitor is on the LDO side of the 1kΩ resistor, I wouldn't expect to see an issue from the TPS7A02 itself. I'd expect Vin of the LDO to be approximately 2.3V with a 1mA load, which should be outside of dropout for a 1.5V output. Is the 1mA load a transient draw during startup, or is it steady-state? Can you confirm input and output voltages of the LDO?

    Best Regards,

    Alex Davis

  • 0 in reply to Alex Davis
    Prodigy 10 points

    Hi Alex,

    Thank you for your response. The 4.7uF is on the LDO side of the 1k resistor. It goes 3.3V battery-1k resistor-4.7uF to gnd-then LDO. There is no load on the LDO so it should not be drawing 1mA. The LDO is 30nA or so as per the data sheet. The drop across the 1k should be in the uV range but for some reason the LDO is drawing 1mA with no load. It is not a transient it is steady state at 1mA. The prevailing theories at this point are that the LDO is unstable for some reason or the LDO draws significantly more current in drop out conditions hence causing a latch up scenario with the 1k resistor. There are no observed instability indicators when scoping the LDO. We have assembled several boards and are seeing this behavior consistently.

    Thank you,

    Nathan

  • +1 in reply to Nathan Carter
    TI__Genius 12240 points

    Hi Nathan,

    TPS7A02 shouldn't have a dramatic increase in quiescent current even in dropout (see datasheet figures 6-1 and 6-2). 

    But with a 3.3V supply voltage, 1kΩ source impedance, and 1mA of input current into the LDO gives an input voltage of around 2.3V. The worst-case dropout voltage for a 1.5V output at 200mA load is 560mV, meaning that the LDO should not be in dropout if its input voltage is above 2.06V. A 2.3V input should have enough headroom above that dropout threshold that the LDO shouldn't be in dropout. 

    Can you check input and output voltages on the LDO? Ideally both a DC measurement with a DMM and an AC measurement with an oscilloscope. As an experiment, can you swap the 1kΩ resistor to 100Ω?

    Best Regards,

    Alex Davis