Tool/software:
Hi team,
Our customer is evaluating this device with EVM. In 2.4.3 Charger Mode Verification section, set-up Single-bit registers should be below figure after 2.2 Hardware Setup.
In this figure, VSYS_STAT is "Not in VSYSMIN regulation (BAT>VSYSMIN)". But as following 2.4 test procedure, VSISMIN is set 3520mV, and in 2.2 Hardware Setup, Load #1 is set 2.5V as VBAT.
So, in these setting, BAT is below VSYSMIN and VSYS_STAT become "In VSYSMIN regulation (BAT<VSYSMIN)".
Is my understanding is correct?
The customer wondering VSYS_STAT is said should be "Not in VSYSMIN regulation (BAT>VSYSMIN)" in this section.
Best regards,
teritama