UCC27714: How to Optimize Dead Time for UCC27714 Push-Pull Driving?

Hello,

Thank you for the interest in the UCC27714 half bridge driver. For the 1st question, the optimum dead time range is very dependent on the specific design details, including the Mosfet switching properties and gate charge and the operating conditions of the converter. 

In a push pull design, I believe the dead time will be determined by the controller to achieve the target output voltage, and will be dependent on the DC voltage input, turns ratio of the transformer and output voltage. In all but low voltage DC input I would expect that there would be considerable dead time determined by the PWM control pulse width to achieve output voltage regulation.

Regarding achieving a minimum dead time to account for maximum duty cycle at low input voltage, the converter power stage should be optimized to ensure the Vgs of the two Mosfets do not overlap on the switching edges to avoid cross conduction. Also another consideration is to make sure there is margin to account for the driver delay matching parameters, tPDRM & tPDFM, of 20ns. Add 20ns margin minimum to account for timing variations. For EMI typically what impacts the EMI is the switching dV/dt which can be optimized by selecting the gate resistance to reduce dV/dt and ringing. EMI and switching losses is typically a tradeoff specific to the converter power train and parasitic elements such as stray capacitance on the switch node and parasitic inductances. 

Regards,