TPS544C26: Alert pin is low

Hi Saddhi,

1. Is ALERT# normal without probing the ALERT# pin? If yes, it may be caused by oscilloscope probe. Usually we use differential probe to probe SVID signal.

2. You said ALERT pulls up to 1V with 50ohm resistor, Where is that 50ohm resistor location? Per Intel PWM spec as below, That 50ohm resistor should be placed at the CPU side, not VR side. Also there is 200ohm series resistor on the CPU side too. Could you please check if your SVID signal follow the Intel "Daisy-Chain".

3. The SVID bus is a high-speed data bus and proper bus routing should be done to avoid cross talk  or noise coupling.  Please  check your PCB layout of SVID signal routing, Route SDIO line between SCLK and ALERT# lines. Keep>60mil clearance from any 12Vin traces/coppers/vias and any switching nodes. Must check all the ways from VR side to CPU socket. If ALERT# picks up some noises, it will cause it abnormal. Please refer to Intel document #544905

Hope this helps,

Thanks,

Nancy

Hi Nancy,

1. We probed the SVID CLK, DATA & Alert pins for this IC. We are getting logic high voltage for SVID CLK and SVID DATA pins. But, for Alert, we are getting logic low. Please check the below attached image. 

2. Yes, 50ohm pullup resistor is placed near CPU Side only as per Intel recommendations. 

3. Yes, we have followed the routing guidelines for SVID signals as per Intel guidelines. We have not modified anything as compared to reference design from Intel.

Hence this might not be the issue.

Thanks,

Siddhi

Hi Siddhi,

From your waveform, it seems ALERT# could not pull up to high. Is ALERT# always low? Or just after you adding probe on that? What is condition which you notice ALERT# is low? During power up or some SVID events? What is SVID event? In below cases, the ALERT# will assert. Please check you condition.

Otherwise, please send me the TPS544C26 config file, schematic and your PCB layout.

Hope this helps,

Thanks,

Nancy

Hi Nancy,

Yes, the Alert is low from beginning. 

We have probed all three SVID signals(CLK, Data, Alert) and powered on the board. So after power on, CLK and Data is logic high, but Alert is logic low(approx 120mV) as seen in waveform which we shared earlier. 

When we are reading Status1 register (10h) from UPDT, we are getting 1 as output which indicates VR_Settled and there is no IccMaxAlert or ThermAlert fault.

But, when we tried to clear Alert using UPDT, then after this Alert pin is going high. 

Can we connect over mail for sharing schematic & config files?

Thanks,

Siddhi

Hi Siddhi,

The TPS544C26 behavior is normal. ALERT# will pull low after VR settled which means VR output reached the target. The system should issue "GetReg 10h" command to clear ALERT# after power up. See below.. No need to send schematic/layout and config file. 

Thanks,

Nancy

Hi Nancy,

We checked the Status1 register using UPDT, and we are getting 1.

But when we are checking BAh register in Fusion (I2C Device GUI), we are getting 0.

When we are checking the output voltage using multimeter and also in Monitor tab using Fusion, we are getting 1.8V which is expected.

Then why we are getting 0 in BAh register?

Can this be the cause for Alert to stay at logic zero?

How this can be corrected? 

Thanks,
Siddhi

Hi Siddhi,

After you power up, first check I2C 0xBAh first, it should be 1. Then if use SVID GetReg 10 command, it will clear VR_settled bit from 1 to 0.

Please try it.

Thanks,

Nancy

Hi Nancy,

We have checked the BAh register after power up.

The VR_Settled bit is 0 for us. Even though we are getting correct Vout, this bit remains 0.

Thanks,

Siddhi

Hi Siddhi,

Thanks for pointing this out. The 0xBAh I2C register is a direct copy of the bits of SVID_STATUS_1 register and should not affect your application as long as SVID register 0x10h behavior is correct. I will check with the team and let you know once I have an answer.

Thanks,

Nancy

Hi Siddhi,

I will close this post. we can communicate offline. nancy_zhang@ti.com.

Thanks,

Nancy