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HD3SS3220: Need inputs on the design

Part Number: HD3SS3220

Tool/software:

Hi Team,

We are using this DRP part in our design. Kindly review the schematic.

HD3SS3220IRNHT

1) whether this IC needs any power control switch?

2) The Vbus_det pin can be directly connected to 5V supply with 900k resistor right? is there anything to be taken care?

3) Current consumption of each rail - 3.3V and 5V? (VDD5 and VCC33)

Regards,

Sathya Priya N

  • Hi Team,

    Waiting for the inputs,

  • Hi Sathya,

    Sorry for the wait on this. I will review this now, and try to get an answer to you by EOD tomorrow, 7/24.

    Thanks,

    Ryan

  • Hi Sathya,

    Would it be possible for you to send the schematic as a PDF or at a higher quality? The picture provided is a little hard to parse, even when zoomed in.

    1) whether this IC needs any power control switch?

    Yes, the ID pin of the HD3SS3220, when configured as a DFP, is used to control when VBUS is sent through the type-C port. If the ID pin does not connect to a VBUS power switch or GPIO of the SOC/MCU controlling VBUS, then the CC negotiation process will only work in one direction, or fail completely. VBUS should only be sent when the ID pin is pulled low.

    2) The Vbus_det pin can be directly connected to 5V supply with 900k resistor right? is there anything to be taken care?

    The VBUS_DET pin should connect to VBUS through a 900KOhm resistor, yes. I would tie it directly to the rail going into VBUS for the type-C receptacle.

    3) Current consumption of each rail - 3.3V and 5V? (VDD5 and VCC33)

    For the 3.3V rail the typ current consumption is 600uA, and for the 5V rail the default power consumption is 70uA, with the level of CURRENT_MODE increasing the current consumption on the rail depending on the level, up ~300uA:

    For pins like the ID pin and OUT/1/2/3 pins, please ensure the pull-ups on these pins are 200KOhm resistors.

    For the RX lanes, you only need 330nF caps on one side of the HD3SS3220, not both. This is to ensure the capacitance of the line is within that 75-265nF range. Please ensure the capacitance through the TX/RX lanes are within that range. We typically recommend 100nF or 220nF caps on the TX lanes, and 330nF caps or no caps on the RX lanes.

    Is this being used as a DFP or DRP? It looks like it is currently configured as a DFP, as the PORT pin is pulled-up. For a DRP application, the PORT pin should be floating, and OUT1/OUT2 should be connected to the device to communicate the detected advertised current.

    Please let me know if you can send a better picture of the schematic.

    Thanks,

    Ryan

  • Hi Ryan,

    Thanks for the detailed inputs.

    We are using for DFP. We will get back to you if anything needed.

    Thanks,

    Sathya Priya N

  • Hi Sathya,

    Got it. If it's a DFP, then the OUT pins can be floating if GPIO mode is being used.

    Please let me know if there are any other questions!

    Thanks,

    Ryan