LM5176: Schematic review

Hi Che Wen,

(In below list items which should be checked again have been marked bold) (Note: other info are left here to give an overview of what has been checked)

Quickstart Calculator:

• Note: I did not check all values to match schematic, reference for the review are the values in the Quickstart calculator
• Slope compensation much lower then suggested
• Phase margin is a little bit low but should be also checked in the real design to consider all parasitics
• Estimated inductor loss is very high for lowest input voltage - this will overheat the inductor
• Also the losses in the MOSFETs are expected to be very high
• Peak inductor current is ~ 31A but inductor saturation is given as 32A - This is already very close

Schematic:

(In below list items which should be checked again have been marked bold)

• Series Resistor with 2k at VISNS (required if Vin > 40V but recommended for all conditions as VIN can also go higher during bursts, only LM5176)
• BIAS connected  - not sure where DCin is
  If BIAS is not used connect to GND or VIN (do not keep open) - BIAS max = 40V !
• MODE: allowed Resistor
  (LM5176 only 93k1 or 200k or Vcc)
• Cap at VCC
  Cap at VCC large enough - check ratio to Boot Caps (at least 5)

• Snubber on SW1 and SW2 
  Place Footprint for a snubber at SW1 and SW2
   (they can then be populated in case needed (e.g. due to EMI) without layout change)
  Note: Snubber R connected to GND not Inductor for better Thermal performance

• Snubber connected to PGND not to Sense Resistor
  -> do not connect to Sense resistor to avoid snubber current injection into Sense signal
• Add Series Resistor into MOSFET Gate signals lines
• (they can then be replaced in case needed (e.g. due to EMI) without layout change,
  additional option: add a diode in parallel for slow on and fast off.
• Gate resistors are <=5 Ohm
• Voltage rating of MOSFET
  (Have a margin of 30% is recommended)
• Use Kelvin connection for Current Sense (CS/CSG) to LM5176
• Filter at CS/CSG:  tau < T/200
• Cap at EN/UVLO
  Adding a Cap to the low side resistor of the EN/UVLO can help to avoid ripple in startup esp. of very low startup voltage is selected
• UVLO setting relative to lowest input voltage
  UVLO is set to 6V but operating range starts at 9V - relative large distance

• ISNSP/N shorted and connected to GND if not used

• Select the suggested capacitor for slope compensation. Preferable next lower instead of higher value (= more slope compensation)
• Please check phase margin over the full range (recommend > 60 Degree)

Layout (for reference only)

(In below list items which should be checked again have been marked bold)

• Vcc Cap close to pins
• AGND and PGND connected at Thermal pad - yes
• Via's in Thermal pad: Thermal Pad could get more via's to better distribute power loss of the LM5176
• AGND island
    -> a AGND power area help to avoid disturbances injected into the AGND related components
• Kelvin connection to CS/CSG sense resistor -> CSG should have dedicated wire to sense resistor not via ground plane
• Kelvin connection to ISNS+/- sense resistor (shorted to GND if not used)
• Small current loop for HDRV1/SW1 (area enclose by this wires should be as small as possible - best to have both on top of each other)
• Small current loop for HDRV2/SW2 (area enclose by this wires should be as small as possible - best to have both on top of each other)
• Input caps close to MOSFET
• Output caps close to MOSFET
• FB divider close to LM517x

PDF link:
Additional info on layout can be found here :

(1) Four-switch buck-boost layout tip No. 1: identifying the critical parts for layout

(2) Four-switch buck-boost layout tip No. 2: optimizing hot loops in the power stage

(3) Four-switch buck-boost layout tip No. 3: separating differential sense lines from power planes

(4) Four-switch buck-boost layout tip No. 4: routing gate-drive and return paths

Best regards,

 Stefan