Other Parts Discussed in Thread: EV2400
Tool/software:
Hello Ti Team,
I am using the STM32U535RET6 as the host controller to communicate with the BQ7697204 AFE via SPI, using CRC-enabled transactions. The host SPI clock is configured at 1.25 MHz.
The SPI transaction sequence is as follows:
SPI_SLAVE_SELECT(RESET);
HAL_SPI_TransmitReceive(&hspi2,SPI_Tx,SPI_Rx,3,HAL_MAX_DELAY);
SPI_SLAVE_SELECT(SET);
delay_us(800);
SPI_SLAVE_SELECT(RESET);
HAL_SPI_TransmitReceive(&hspi2,SPI_Tx,SPI_Rx,3,HAL_MAX_DELAY);
SPI_SLAVE_SELECT(SET);
For example, to read CellVoltage1, I send the address bytes 0x14, 0x00, and a CRC byte in the first transaction, and then repeat the same transaction to receive the voltage data.
When I reduce the inter-transaction delay to 200 µs or 500 µs, the readings from the AFE become highly unstable and vary frequently. Even with an 800 µs delay, I still observe occasional abnormal values, but they are significantly less frequent compared to the shorter delays.
Since my AFE read task runs every 100 ms and I need to fetch all 16 cell voltages, 3 temperatures, current, and various status registers, a huge delay like 800µs to 1000 µs or higher adds considerable overhead, which is not acceptable for my application.
I would appreciate guidance on how to reduce this inter-transaction delay without compromising the reliability of SPI communication with the AFE.
Best Regards,
SAI VARUN.
