• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 63 subscribers
  • Views 159 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMR51440: LMR51440 Switch node rising edge weird shape, radiated emissions concern

Amit Halfi
Prodigy 70 points
Part Number: LMR51440

Tool/software:

Hi,

As a part of the Proof of Design I am performing on my custom HW, which utilizes LMR51440SDRRR to convert 24V to 5V,

I measured the switching node between the LMR51440 and its inductor. The rising edge has a weird shape.

The voltage rises about 80% of Vin, then drops to 60% of Vin, then rises and finally reaches Vin (+minor overshoot). See image.

The falling edge does not show this phenomenon. See image.

Increasing the load on the buck output from ~0.6A to ~3.6A causes the peaks to grow farther apart (80% vin -> 90% vin, and 60% vin -> 20% vin).

Increasing the boot capacitor from 100nF does not make a visible difference.

Adding a series resistor (0.5 Ohm - 2.7 Ohm) to the boot capacitor reduces the first peak's value (2.7Ohm causes ~70% of vin), but does not change the overall shape.

Adding a snubber (100pF, which is as large as I can practically add regarding power dissipation) to the switch node increases both peaks voltage levels and causes an overshoot and ringing. It does not change the overall shape. It also adds ringing to the falling edge, which is unwanted because it looks fine.

I'll emphasize that this is not an issue by itself. The buck operates correctly, it is stable, and all is well.

I fear that, in the nearby future, when I take my custom HW to the lab to measure its radiated RF emissions, I will see it radiating strongly.

My questions are:

1. Does the EVM of the LMR514x0 show a similar weird shape on its switch node rising edge?

2. Do you have a theoretical explanation for this shape? For example something related to the high side switch driver method of operation, insufficient high frequency vin capacitors, etc.

3. Do you think this shape is just an artifact of my measurement setup? 1GHz scope, 500MHz probe, taken with a small GND spring as shown in image.

4. If you manage to recreate this on the EVM, do you consider this as an issue? If so, how do you propose to solve it?

Thank you.

  • 0
    TI__Mastermind 24165 points

    Hi,

    Are you able to share your layout and your schematic? I can take a look at these to see if there is anything out of the ordinary.

    In addition, are you able to order the EVM for this device? It will be helpful to do an ABA swap that would give us a clear understanding of if it is an IC issue or an application issue (board and test setup). I do not see anything you are doing incorrectly in how you are measuring SW, but the ABA swap would help us rule this out.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 70 points

    Hi Joshua, thank you for your response.

    The design mostly follows TI's recommendations. See attached image for layout.

    Schematic description:

    1. pin RT shorted to GND (SW frequency measured ~860kHz + spread spectrum).

    2. input capacitors 100uF electrolytic (not shown in image) + ~20uF bulk MLCC after derating + 100nF 0402 + 1nF 0402. MLCC As close to the IC as possible.

    3. boot cap 100 nF 50V

    4. inductor 4.7uH nominal, RDC 40mOhm max, I saturation 10A (20% inductance drop)

    5. output caps ~70uF bulk MLCC after derating + 100nF 0402 + 1nF 0402. As close to the inductor and input caps as possible. other capacitances are farther away.

    6. The EN subcircuit enables the buck at vin = ~18V, which means it is probably not related.

    Unfortunately I cannot perform an ABA swap with an EVM, but I measured the same phenomenon on more than one board.

    Perhaps you could access and EVM and check if you measure the same phenomenon? I'm aware the layout, the surrounding components, and even the specific IC part number are different, but I still think theres value in recreating the same measurements in a different setup.

    configuration: 24V input to 5V output, 0.6A load.

  • 0 in reply to Amit Halfi
    TI__Mastermind 24165 points

    Hi Amit,

    Looking through your layout, I do see a couple notes of improvement that are also likely to affect the SW node ring. 

    • There are thermal reliefs on the input, SW, and GND traces. This overall increases the inductance/impedance between the components connected to these nets and their pins. Each of these thermal reliefs has the potential to create the ring seen on SW.
    • Are there other layers on the board that are not shown?

    We can do an EVM check for this device. I will provide waveforms by the end of the week.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 70 points

    Thank you, Joshua.

    Regarding other layers, there are several more layers in the board. In this section of the PCB, there are only GND layers and the output power layer. There aren't even any signal traces.

    The bottom layer has more input and output bulk MLCC caps (exactly under the top bulk caps), and the HF output caps (marked in the above image).

    The feedback trace is also pulled from the bottom, back towards the components on top.

    Please keep me updated on the EVM check.

    Also, regarding my previous question #2:

    Amit Halfi said:
    Do you have a theoretical explanation for this shape? For example something related to the high side switch driver method of operation, insufficient high frequency vin capacitors, etc.

    Do you have any theoretical explanation which could explain this signal shape?

    Thank you

  • 0 in reply to Amit Halfi
    TI__Mastermind 24165 points

    Hi Amit,

    I will source a board and get back to you with that. Theoretically, any extra impedance/inductance on the SW node can affect the SW node ring.

    Are you able to send those layout files for review?

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 70 points

    Hi Joshua,

    I cannot share the layout files.

    Have you received the EVM?

    Thank you, Amit.

  • 0 in reply to Amit Halfi
    TI__Mastermind 24165 points

    Hi Amit,

    Yes, I have a board now and should have some data for you by the end of the week.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 70 points

    Hi Joshua, I hope you are doing well.

    Were you able to recreate the strange rising edge phenomenon on the EVM?

    24V input, 5V output. Higher load worsens the phenomenon.

    Thank you, Amit

  • 0 in reply to Amit Halfi
    TI__Mastermind 24165 points

    Hi Amit,

    Sorry for the delay. On the EVM, I do see a first "pulse" on the SW node at a 600mA load. However, as load increases, this pulse disappears, so this looks to be a factor of light load PFM operation for the device. At 3.6A, the SW node waveform only has a rise to VIN (+minor overshoot) without a preemptive pulse.

    However, in reading your phenomena, you did note that the device still experienced this SW node ring at a 3.6A load. Are you able to share what this waveform looks like at 3.6A?

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 70 points

    Hi Joshua,

    Increasing the load from 600mA to 3.6A emphasized the phenomenon. Attached image is with 3.6A load.

    Since the opposite happened on the EVM, I'm led to believe the cause of the phenomenon is an issue with my layout.

    I'll reconsider my options, and if I'll have any more questions I'll let you know.

    Thank you.