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UCC27201: Possibility of component destruction

Part Number: UCC27201

Tool/software:

Hi team,

What are the chances of component breakdown under the following conditions?
I thought there would be no problem because the absolute maximum ratings are covered, but I would like to confirm this because destruction has occurred with no known cause.
1: If the VDD voltage falls below the recommended operating voltage (8V or lower), is there any problem if a 5V drive signal is input to the HI and LI pins?
2: Regarding the first question, if the voltage drop is extreme and for a short period of time (tens to hundreds of us) the voltage between VDD and VSS becomes less than the HI and LI pin input voltage, will this affect the IC?

Best Regards,
Ryu.

  • Hi Ryu,

    1. If the VDD falls below the recommended operating voltage, 8V or lower, the device will stop and wait until there is 8V due to the 8V UVLO. Also, there is no problem if a 5V drive signal is input to the HI and LI pins, but the UVLO will hold HO and LO low. If your application does not need full performance, you may be able to use lower voltages. For further details explaining UVLO and using lower voltages, here is an application report:
      1. Understanding Undervoltage Lockout in Power Devices (Rev. A) (5.1 Recommended Operating Conditions). 
    2. If the voltage drop is extreme and for a short period of time such that the voltage is less than the HI and LI input voltage, the IC should be fine as long as the IN min/max limits are not exceeded. 

    What exactly is breaking/failing? What are the conditions on all pins when this happens, and do you have any schematics or waveforms? Have you done an ABA swap?

    Best Regards,


    Suzuko Devine

  • Hey Ryu,

    To clarify some of Suzuko's response here, see below:

    1. As she mentioned, if VDD falls below the UVLO thresholds (8V), the device will pull the outputs low irrespective of the inputs. The input voltage rating is independent of the VDD voltage and therefore having HI/LI amplitudes greater than VDD should not cause damage.

    2. For these drivers, us is a longer period as they operate on the ns scale with minimum pulse widths of 40ns. So, if VDD falls low for this long of duration, UVLO will occur but damage is not expected due to HI/LI being higher than VDD.

    Please measure a damaged IC and a good IC pin impedance with respect to VSS with the IC off the PCB and on the bench.

    Thank you,

    William Moore