This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ41Z90EVM: BQ41Z90 Setup to turn on CHG and DSG FETS

Part Number: BQ41Z90EVM
Other Parts Discussed in Thread: BQ41Z90, BQ40Z80, BQSTUDIO

Tool/software:

Hi,

I am busy working with the BQ41Z90 EVM. I am currently struggling to get the charge and the discharge fets to turn on. I have set up the data memory as far as I could but I am unsure if there is something I am missing that keeps the fets from being able to activate. 

I have attached the Data Memory files as well as an image of the registers. I would greatly appreciate any assistance in this matter.

Kind Regards
Marco



1212.Registers.gg.csv

  • Hello,

    This question has been assigned and will be reviewed when possible.

    Thank you,
    Alan 

  • Hi,

    You have FET_EN =1, this means the FW will control the FETs.

    Please set NR=0, disable all protections and send a reset cmd, your fets should then close.

    Regards,

    Diego

  • Hi Diego, thank you for the reply.

    Unfortunately, this did not resolve my problem I am still unable to toggle the fets, NR was already set to 0 under the DA configuration and I would also like to use and test the protection I set up so I would prefer if it remains enabled but I am unable to toggle the fets with it enabled or disabled.

    Some more information regarding the setup. I am using a 6s Lithium-ion battery pack, that I have successfully used on a BQ40Z80 thus using it again as a reference, with a chemical ID (0x2152) that matches it closely. Each cell has a typical capacity of 4000mAh and a minimum of 3900mAh, a nominal voltage of 3.7V, a standard charge voltage of 4.2V and a cut-off voltage of 2.5V, the standard charge current is 2A and max continuous discharge current of 35A. The cells have been connected correctly according to what the EVM suggests.

    It seems that after the recommended changes have been made the registers show a few different bits that have been set high or low, REST low, RDIS high and RTA high. Here is an updated image.



    Kind Regards
    Marco Moller

  • Hi,

    Thanks for the information, what FW version are you using?

    Regards,

    Diego

  • Hi, 

    The installed FW is 0.02 (the image also shows 0x0002), I am unsure of the precise version, and I downloaded it the 20th of June 2025.

    Kind Regards
    Marco Moller

    Update: I just updated the FW to the latest on the website and I still have the same problem.

  • Hi Diego,

    From what I can see the problem lies with the TDA and TCA bits which are set. This is caused by PRESS = 0. I read in the TRM that the PRESS functionality is determined by the NR bit but no matter what I make NR, PRESS remains 0.

    I tapped the test point on pin 43 with a scope and confirmed the sampling every 250ms is not being pulled down to ground. When I force it to ground via a physical connection the PACK voltage is present. How would I fix this in the configuration.

    Kind Regards
    Marco Moller

  • Hi,

    Can you pull your bq.fs and share it here.

    Regards,

    Diego

  • Hi Diego,

    Please find attached the bq.fs file.

    Kind Regards
    Marco Moller
    TEST.bq.zip

  • Hi,

    Thanks please allow me sometime to look into this.

    Regards,

    Diego

  • Thank you Diego, I look forward to hearing from you.

    Kind Regard
    Marco

  • Hi,

    I have not had a chance to test your configuration yet. However, here are the complete steps to close the FETs that have helped many customers.

    Board set up

    Series

     

    Parallel

    BQstudio settings

     FET_EN = 1

     

    This can be toggled with the FET_EN cmd on the right

     

    FET Options = 0000

    Data memory -> Settings -> FET options

     

    NR=1

    Data Memory -> Settings -> DA configuration

     

    Disable Protections

    Make sure all protections are disabled, all protections should =0, notice some bits are rsvd, these can be left as is. These bits are described in the TRM.

     

    Regards,

    Diego