TPS1211-Q1: Making sure EN/UVLO behavior

Hi Kazuki,

Is the goal to turn off the FETs or to put the device into low IQ shutdown mode?

The EN/UVLO pin is typically not used as the trigger to turn FETs on and off. When EN/UVLO is pulled high, the charge pump turns ON and charges the BST capacitor; it can also be used to set the undervoltage lockout threshold. The INP pin is used to turn the FETs on and off by controlling the state of the PU/PD pins. 

Thanks,

Rishika Patel 

Rishika-san,

I understand you don't recommend to use turn-on/off FET by EN/UVLO pin.
Anyway, could you please answer following question to understand this device's behavior?

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Then, we'd like to make sure this device's behavior.

In normal operation, they will apply HIGH signal(approx. 3.3V) at EN/UVLO pin from MCU to turn-on FET.
Once TPS1211-Q1 detect fault, MCU detect this fault event and drive EN/UVLO to Low.
However, their MCU's LOW level approx. 0.4V which is higher than VENF(0.3V) so I'd like to make sure just in case.

In this condition, LOW signal from MCU is still lower than VUVLF(1.1V) so TPS1211-Q1 turn-off FET.
However, Low signal is higher than VENF so we cannot guarantee this device enter low Iq mode.
Is this understanding correct?

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Best regards,

Kazuki Kuramochi

Rishika-san,

Customer's expectation is to completely shutdown TPS1211-Q1 once fault is detected.

The datasheet said above UVLO threshold cause turn-on device completely(charge pump, GD, protection, diag)

Also Lower than EN cause shutdown device completely.

However, there isn't device mode description between lower than UVLO and higher than EN.
Then, could you please tell me how work this device during this condition?

Best regards,
Kazuki Kuramochi

Hi Kuramochi-san,

Yes, your understanding is correct. To guarantee that the device enters low IQ shutdown mode, please ensure that the voltage at the EN/UVLO pin is less than the minimum defined for V(ENF).

Thanks,

Rishika Patel 

Rishika-san,

Could you please explain about the device status and behavior during EN/UVLO voltage is lower than V(UVLOF) but higher than V(ENF)?

As far as I confirmed, there isn't description for this status.
The datasheet said only device will fully turn-on when EN/UVLO voltage become higher than V(UVLOR) and device will enter low Iq mode when EN/UVLO voltage below V(ENF).

We need information for the middle condition.

Best regards,
Kazuki Kuramochi

Hi Kuramochi-san,

In order for the low IQ effect to be in place, VEN/UVLO<V(ENF). If not, the device will be considered in active state, but the gate driver section will not be activated because it has not met the V(UVLOR) threshold so it should require around normal IQ. 

Thanks,

Rishika Patel 

Hi Rishika-san,

Thank you for your confirmation.
I'd like to dig into more about V(ENF)<EN/UVLO<V(UVLOF) condition.
In this condition, are you saying PD/PU_OFF and G_OFF happen?

Also, how about IMON?

Datasheet said TPS12111-Q1 disable IMON during PD_OFF but block diagram seems it need to be lower than V(ENF).

Also, is there any other feature or function which will be disabled by V(ENF)<EN/UVLO<V(UVLOF)?

In other words, PD/PU_OFF and G_OFF are only event which is caused by V(ENF)<EN/UVLO<V(UVLOF)?

Best regards,
Kazuki Kuramochi

Hi Kuramochi-san,

Sorry for the delay, I will check with the team.

Thanks,

Rishika Patel 

Rishika-san,

Sorry for rushing you but is there any update?

Best regards,
Kazuki Kuramochi

Hi Kuramochi-san,

I am checking on this with the systems team and should have an update tomorrow. Sorry for the delay!

Thanks,

Rishika Patel 

Hi Kuramochi-san,

I checked with our systems engineer and for this in-between condition, some circuitry may be on and some may be off. We cannot guarantee which blocks will be on versus off because generally speaking this is just a range - V(ENF)<EN/UVLO<V(UVLOF), we would need to know the exact value of EN/UVLO. So, the IQ will be slightly lower than the active mode IQ during this condition. 

Thanks,

Rishika Patel 

Rishika-san,

Below is my understanding summary for the device behavior during V(ENF)<EN/UVLO<V(UVLOF).
Is this correct understanding?

1. PD/PU pin and G pin will be Low(short to SRC) or Hi-z.
2. Some internal block may be on or off. we cannot guaranty what block will be on or off.
3. So Iq may be fluctuated.
4. However, Q1 and Q3 should be off and VBATT will be disconnected from VOUT side regardless of internal block condition due to the status of 1..

Best regards,
Kazuki Kuramochi