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Original question:

UCC21710-Q1: time delay before OC pin is activated

UCC21710-Q1: Issue of UCC21710-Q1

Mohammed Saquib
Prodigy 40 points
Part Number: UCC21710-Q1

Tool/software:

Hi Ti Team,

I got one issue with this gate driver (UCC21710-Q1) as I am using gate driver for providing gate pulses to 1200V Mosfet (AIMCQ120R030M1TXTMA1) when I am switching my gate driver above 100V i am observing my gate driver is disabling automatically by taking some current. and below 100V I am observing the sin wave in gate pulse and this thing i observed only on high side Mosfet gate driver. so i disabled the OC pin and AIN pin (pulled to GND) even though if it is disabed means I am not getting any pulses of +!5V and -4V. so give me any solution. what to do I am attaching my schematic of gate driver circuit.

  • 0
    TI__Expert 8075 points

    Hi Mohammed,

    Thanks for explaining the details. The schematic looks overall good. i don't see any major issues. Is it possible to capture the waveforms during the FLT the following signals,

    DESAT , GATE, INP, FLT , please use high BW scope and probe and probe the signals as close as possible to the device.

    Thanks

    Sasi

  • 0 in reply to Sasikala Thangam
    Prodigy 40 points

    Hi Sasikala,

    As mentioned, we observed the following. Please go through the same and let me know if any updates.
    DESAT: Low
    GATE(OUTH, OUTL): Low
    INP: (High: Low) As expected.


    Attached routings snap FYR.

  • 0 in reply to Mohammed Saquib
    TI__Expert 8075 points

    Hi Mohammed,

    I am interested to see the FLT low going instance and the delay between OUT and FLT. So can you please share the scope capture.

    In the provided layout, there are no marking of any component, so its hard to process, can you please share the component names along with the layout.

    Thanks

    Sasi