• State Resolved
  • Replies 14 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 167 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TPS3851: the wave of WDI signal

chunli Liang
Prodigy 210 points
Part Number: TPS3851

Tool/software:

Hello TI Support,
I have a problem with the TPS3851G18EDRBR (extended timing version). 
Part number: TPS3851G18EDRBR.
VDD voltage: 1.8V.
CWD capacitor: 5700pF (5.7nF).
tWD(watchdog timeout):496.2ms(Typ),345.8ms(min)~685.9ms(max)
SET1 : SET1 is connected to  HIGH(1.8V ).
When I was testing, I noticed the following phenomenon. Is this phenomenon normal？
Please refer to the following wave.
The WDI signal has a small 100mV change(0→100mV or 100mV→0).
But it’s always lower than VIH (VIH=0.8*VDD=0.8*1.8V=1.44V),also lower than VIL(VIL=0.3*VDD=0.3*1.8V=0.54V).
However,after WDI changes 100mV→0 about 496ms (tWD(watchdog timeout):496.2ms(Typ)), the WDO signal goes low,and reset. This keeps happening over and over again.
Because there is no WDI change in tWD(watchdog timeout).
The WDT timeout is between 345.8ms(min)~685.9ms(max).
From the time of the RESET is pulled high to the time the WDO is pulled low, the time is 700 ms, which is longer than the WDT timeout 345.8ms(min)~685.9ms(max).
The time is longer than 345.8ms(min)~685.9ms(max).
Based on the above picture, I believe WDI changes 100mV→0 has been effective.
Is that right?
Thanks and Best Regards
Chunli Liang
  • 0
    TI__Genius 11580 points

    Hi Chunli,

    Could you help to share a schematic of the TPS3851G18EDRBR? And could you please also have the VDD in the scope capture aswell. I would like to understand why the RESET is asserting and remaining asserted.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    Prodigy 210 points

    Hi Joshua

    Please refer to the circuit (as it is provided to the outside, it has been slightly modified, but it does not affect the logic).
    For self reset,the WDO pin and MR pin are connected together here.

    Add VDD. And added test points on the waveform diagram.

    Additionally, by the way, the slight change in WDI (0 → 100mV or 100mV → 0) is due to the WDI pin being connected to the IO of the FPGA. During the FPGA configuration process, it is 100mV, and after the FPGA configuration is completed, it is 0V.

    Thanks and Best Regards

    Chunli Liang

  • 0 in reply to chunli Liang
    TI__Genius 11580 points

    Hi Chunli,

    Thank you for sharing the schematic.

    I now see why the reset is asserting, but I will need to test this WDI behavior in lab. I will provide and update tomorrow 8/15 PST.

    Thanks,

    Joshua

  • 0 in reply to Joshua Garcia
    TI__Genius 11580 points

    Hi Chunli,

    Apologies for the delays but we do not have any evaluation boards on hand (TPS3851EVM-780). I have placed the order for them and based on typical ship time 3-5 days they should arrive late next week.

    Thanks,
    Joshua 

  • 0 in reply to Joshua Garcia
    Prodigy 210 points

    Hi Joshua

    Thank you for your support.I am waiting for your evaluation results.

    Thanks and Best Regards

    Chunli Liang

  • 0 in reply to chunli Liang
    TI__Genius 11580 points

    Hi Chunli,

    Happy to help I will keep you up to date with the results as I get them.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    TI__Genius 11580 points

    Hi Chunli,

    I have not received the EVMs yet, but I have followed up with the planning/shipping team to get more details here. I will keep you updated.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    Prodigy 210 points

    Hi Joshua

    Thank you for your support.Please help me to resolve the question.

    Thanks and Best Regards

    Chunli Liang

  • 0 in reply to chunli Liang
    TI__Genius 11580 points

    Hi Chunli,

    I now have the units and EVMs in hand. I will perform the tests by end of day today PST and share my findings.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    TI__Genius 11580 points

    Hi Chunli,

    I have not concluded the tests yet, I will test further and provide an update tomorrow.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    TI__Genius 11580 points

    Hi Chunli,

    I have tested a TPS3851G30EDRBR IC I had on hand with the EVM and found that when having a voltage amplitude on the WDI below ~50% the WDI does not recognize it as a proper transition. Please note I used a 5600pF external capacitor on CWD. See the scope captures below confirming device operation:

    WDI amplitude 1.7V WDO remains unasserted:

    WDI amplitude 1.6V WDO asserts:

    I also tested both of these in the configuration your customer has with MR shorted to WDO and the results were consistent, please see below.

    WDI amplitude 1.7V WDO remains unasserted:

    WDI amplitude 1.6V WDO asserts:

    I believe that there is some additional parasitic capacitance as well as capacitor tolerance that is allowing the watchdog to have a timeout period of 700ms. One way you can test this is by grounding the WDI pin and confirming if the system still resets at the ~700ms time.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    Prodigy 210 points
    Hi Joshua,
    Thank you for your previous analysis and suggestions regarding the TPS3851G18EDRBR issue, which provided an important direction for our troubleshooting.​
    In accordance with your guidance, we have completed the test of grounding the WDI pin completely.
    The test result is identical to the previous one: the system still resets periodically, and the interval from RESET release to WDO going low remains at approximately 700ms, which is exactly the same as the phenomenon when WDI was in the low-voltage state during FPGA configuration.​
    This result is confusing to us: when the WDI is stably grounded (0V), there should theoretically be no valid transitions to trigger the watchdog timer, but the actual timeout reset behavior has not changed at all.​
    In fact, we did not mention to you that SET1 is not fixed high but controlled via a switch circuit.
    During testing, we first disable WDT (to avoid continuous reset), then toggle the switch to enable WDT after generating the WDI waveform.
    And the system is reset.
    From the test results in the figure, it can be seen that the timeout time of WDT is correct.
    ※Now I have not the software that controll the interval time of WDI freely.
    tWD ：548.0ms
    I have a new question.
    According to the timing diagram in the datasheet, the WDT time is defined as the duration from the falling edge of the WDI signal to the falling edge of the WDO signal. 
    However, I would like to know:
    is the time from the falling edge of WDI to the falling edge of WDO the same as the time from the rising edge of the RESET signal to the falling edge of WDO("time?"  in the image)?
    In addition, regarding your comment in the previous reply "I believe that there is some additional parasitic capacitance as well as capacitor tolerance that is allowing the watchdog to have a timeout period of 700ms" , we have currently started investigating issues related to parasitic capacitance and capacitor tolerance.​
    If you have other troubleshooting suggestions or need us to provide additional information later, please let us know.​
    Thanks,
    Chunli Liang.
  • 0 in reply to chunli Liang
    TI__Genius 11580 points

    Hi Chunli,

    Yes the Time of one valid WDI falling edge to the WDO falling edge is the watchdog timeout time. This is the same time as the RESET rising edge to the WDO falling edge. To reiterate in other words, the watchdog counter starts once the watchdog is enabled and RESET goes high and the watchdog timeout counter restarts each valid WDI falling edge pulse.

    How many devices and boards have been tested? and how many of those have observed this 700ms timing? My only recommendation would be to reduce the overall capacitance to achieve the desired timeout period.

    Thanks,
    Joshua

  • 0 in reply to Joshua Garcia
    Prodigy 210 points

    Hi Joshua

    I found the reason.
    Sorry, it's our miss here.
    Actually, we also controlled the set pin during testing, and it only becomes effective after the FPGA configuration is completed.
    That is to say, when I first asked you the question,after the reset is released,

    when the small falling edge of WDI, the set pin is also active, enabling WDT.

    So, from that time the WDT start counting. In this way, the timeout time of WDT will be consistent with our design value.
    I'm sorry to trouble you.

    Thanks and Best Regards

    Chunli Liang