• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 73 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS25762-Q1: Issue with booting up on some specific boards

Jesse Kettunen
Prodigy 10 points
Part Number: TPS25762-Q1

Tool/software:

We have few prototype boards where we have implemented TPS25762CA for USB C -connectivity. There are some boards which function just fine, but there are also few which doesn's startup correctly.

Bootup can be easily verified by measuring CC-pins, in the case of not functioning boards the CC-pins will not show any voltage. 

We have tried to find the culprit of the issue by looking into the startup of the chip:

- Internal LDO:s seem to startup fine

Working PCB:

Not working PCB:


Only real difference is that in the working pcb you can see some power usage in 1V5 LDO, which isnt seen on the not working one.

- I2C-connection to EEPROM seems to be fine
By listening to the I2C between PD controller and EEPROM, the data is identical between the boards when comparing it with Saleae.

Is there some easy way to check the ARM core functionality with I2C2?


Below is the schematics of the design:


We have also tested to change the individual chip, but even that didnt fix the issue in the not functioning PCB:s.
What could be the culprit in this case, what should we try to test next.

Would like to have confidence that the design itself is working correctly before moving forward to next revision of the board, this can always be some manufacturing faulty boards.

  • 0
    TI__Genius 11165 points

    Hi Jesse,

    Thank you for the detailed message.  Upon first pass, I don't see anything wildly off in the schematic.  Nothing that would cause a boot failure.

    Here's a few smaller items I caught:

    • I suggest using the D version of the device (TPS25762DQ...) if you plan to certify with USB-IF.
    • I'm not sure if R364 is populated based on the schematic notation.  The TVSP pin needs to see either 5.6k (firmware update mode) or OPEN (boot from EEPROM).  100k may cause the device to boot to TVSP index 1, causing it to depend on an external micro to host the firmware.
    • Please review the COUT + CBUS recommendations in table 9-1 of the datasheet.  This will ensure stability of the DC/DC converter.
    • Please also confirm the voltage ratings of your caps per section 6.4 of the datasheet.
    • Your CC1/CC2 net labels appear to be swapped - this might cause your polarity detection to be inverted and could throw off your USB3 signal chain.
    • The NTC divider circuit appears to use two discrete/fixed value resistors.   This means the NTC voltage won't change with temperature.  This is fine for normal operation, but you lose the ability to reduce power at higher temperatures.
    • You can drop R251/Q15/R360 in the future since PA_LSGD is not used.  You can directly short C324 to the other CBUS caps.

    All of that aside, one failure I suspect is that the "bad boards" are booting into firmware update mode.  This causes the CC pins to expose 5.1k to GND (Rd) instead of ~3.3V (Rp).  This could be caused if "USBPD_FWUP" is high when 762 samples for the resistance.

    What happens if you remove R363 and R364 from a bad board?  Does it boot normally?  Additionally, what happens if you probe "USBPD_FWUP" and "TVSP" with the scope?  I suggest capturing this along with the input voltage or EN/UVLO - whichever you are using to trigger a device reset.

    Thanks,
    Eric

  • 0 in reply to Eric Hartigan
    Prodigy 10 points

    Hi, thanks for the quick reply.

    1. Was planning on using D-version, but A-version was more readily available during manufacturing. Will change to D-version for the end-product.
    2. R364 was populated due to error during the manufacturing file generation, it was populated during first tests, but was removed during debugging. So it hasn't been populated for a while, A-version shouldnt use that, but it was left for the D-version.
    3. Will alter the capacitance for end-product to suite the correct waveforms, mostly there as a place holder for physical reasons. I did do a quick tests removing unnecessary capacitance, but didnt affect anything.
    4. Voltage ratings are fine, maybe on the high side for 1V5 (16V) but that shouldnt affect
    5. CC pin naming was swapped as per usual, but that was fixed for this board in the firmware. With the boards which function we have tested USB3
    6. NTC divider does use upper side NTC resistor, schematic item is a bit misleading. Have also tested by altering the temperature ranges withing the configuration to test if the chip is in some sort of over temperature mode
    7. Will remove those on the end-product

    I was thinking similarly, by measuring resistance with a multimeter we cant see that kind of resistance.

    By removing R363 and R364 from the board, it doesn't change anything. If i probe USBPD_FWUP it stays GND. 
    If i probe TVSP and trigger to EN/UVLO it will show up like this.

  • 0 in reply to Jesse Kettunen
    TI__Genius 11165 points

    Hi Jesse,

    Your waveform looks correct.  That is, the TVSP resistor looks like it will be decoded as OPEN and boot from EEPROM.  One item I wanted to clarify - you said swapping the unit on a bad PCB remains non-functional.  Is the opposite true?  If you take a the IC from a non-working to a working board, does it still work?

    I don't think there's an LDO issue since you mentioned the EEPROM traffic matches.

    Here's a few more ideas to try in order of importance:

    • Ensure the input voltage is above the highest foldback threshold configured in firmware.  Give yourself some margin to ensure you're clear of the threshold
    • Measure the NTC voltage and ensure it is not in a foldback region.
    • Try polling 0x22 over I2C.  Either I2C1 or I2C2 should work fine.  I expect it should ACK the address.

    Regards,
    Eric

  • 0 in reply to Eric Hartigan
    Prodigy 10 points

    Hi,

    • This might have been the issue. It had the default settings which had the falling edge on ~11.XV and the range 2 max power was set to ~5W. I had the configuration set to min 15W, so there wasnt any PDO which was valid. By setting the foldback to < 1V and setting it always have 15W it fixed some of the boards.
    • I did measure the NTC voltage again, and it was approx 1.8 - 2V, so it should have been just fine. Just to clarify, if the thermistor power foldback enable is set to disabled, it doesnt matter?

    Some other boards seemed to possibly have soldering issues, i had in those case uvp_condition_active_low_global flag set, and by measuring the OUT at 200mV at max, and it seemed that the SW1 and SW2 only jumping from 4.XV to 0V. By doing some reworking on the boards these started to work.

    I think there have been a few different issues regarding this, input voltage could have been really close to the power foldback which wanted to drop the power down to a PDO which wasnt configured as possible.

    Need to go through the configuration settings more in-depth, thanks for the help.

  • 0 in reply to Jesse Kettunen
    TI__Genius 11165 points

    Hi Jesse,

    If thermistor power foldback is disabled, correct, the voltage at the NTC pin doesn't matter (assuming within abs max limits).

    Glad things seem to be trending in the right direction!

    Regards,
    Eric