LM5069: Gate Discharge Issue

Gaurav Agrawal

Part Number: LM5069

Tool/software:

Hello,

We use LM5069 to switch 48V into a high capacitance output (~2.5mF) using the CSD19502 MOSFET and a 12mOhm sense res. There is no load at startup except for the cap.

The design uses dv/dt control with a 0.1uF cap, and the PNP discharge circuit as shown in the datasheet. However, in rare cases, we see a residual charge left on the gate pin, thus causing the MOSFET to show low resistance (10-100 ohm) for hours even after the system is powered off. This dissipates on probing the gate pin, and it works fine again.

However, the datasheet shows a 2mA pull down on the gate pin.

Please let us know if something is missed. Circuit can be shared in a private window for review if needed.

Regards

Gaurav

over 1 year ago

0 Avishek Pal over 1 year ago

TI__Mastermind 46880 points

Thanks for reaching out. Please share your schematic.

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Sent out separately, please check.

Thanks

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

I am not seeing anything wrong in the schematic, which may cause this behaviour.

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Hi Avishek,

Thats ok, but we are facing the issue. It seems the gate charge is stuck sometimes after power off and the internal 2mA pull down doesnt work.

Do you think there should be an alternate method to discharge the gate?

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

Gaurav Agrawal said:
Do you think there should be an alternate method to discharge the gate?

There is no alternate method.

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Hi Avishek,

Pls see this post where a separate discharge path for gate is suggested - LM5069: Spurious shutdown with dV/dt circuit and ripple voltage - Power management forum - Power management - TI E2E support forums

Can you direct my query to Rakesh please?

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

Two issues are separate.
That is a separate issue; the gate turns off during high frequency load transient.
Please share VIN, VOUT, and GATE voltage waveforms while the device is turned off.
What is the exact concern? I hope the residual gate voltage is not enough to turn the MOSFET back ON.
If the R119 resistance is removed, is the residual gate voltage not there?

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Hi Avishek,

The exact concern is that the MOSFET drain-source remains short sometimes after power off. When we touch or probe the gate pin, the short goes away. So we suspect the gate retains some charge. If the gate pin is probed for voltage waveform, we wont see the issue anyway.

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

Avishek Pal said:
If the R119 resistance is removed, is the residual gate voltage not there?

Please respond.

Gaurav Agrawal said:
The exact concern is that the MOSFET drain-source remains short sometimes after power off.

What is the output voltage value?

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

If R119 is opened, the output doesnt rise, may be due to the heavy cap at the output.

When drain-source remains short after power off, of-course there is no output voltage. Its just that on the next power ON, the circuit wont work due to an earlier stage protection mechanism.

Can the MOSFET Ciss also cause the residual charge left on gate after power off?

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

Gaurav Agrawal said:
Can the MOSFET Ciss also cause the residual charge left on gate after power off?

Hopefully not, we have never seen this in our EVM.

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Hi Avishek,

Referring to this issue again, Vin = 50V, Capacitive load after MOSFET = 2250uF.

When the power is switched off, please see attached the waveform. At the time when UVLO is cutoff, the gate is pulled down with 2mA for a sharp cutoff till Vin falls to 25V. But after that the gate dies slowly, following the MOSFET source voltage. We are not clear on this, as the LM5069 should remain operational down till 9V as per datasheet, keeping the 2mA PD active. Can you please check?

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

At the instant, VIN goes below UVLO threshold, ~ 2mA gate pull down current makes the MOSFET VGS close to zero to turn off the MOSFET. After that the MOSFET source pin (COUT) gets discharged through the gate pull down current and MOSFET gate and source follow each other.

At the point marked in a RED cross in the image below, VIN becomes less than 9V, the device loses the input power.

0 Gaurav Agrawal over 1 year ago in reply to Avishek Pal

Intellectual 770 points

Hi Avishek,

We assumed that the MOSFET source would discharge back into the drain side through the body diode once the MOSFET is OFF.

If Cout discharges through the gate, is it also possible that some charge retains on the gate due to the heavy Cout value, thus causing spurious MOSFET turn-on when powered off?

Regards

Gaurav

0 Avishek Pal over 1 year ago in reply to Gaurav Agrawal

TI__Mastermind 46880 points

Gaurav Agrawal said:
If Cout discharges through the gate, is it also possible that some charge retains on the gate due to the heavy Cout value, thus causing spurious MOSFET turn-on when powered off?

This may happen. However, I have never seen in the EVM.