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UCC5390-Q1: UCC5390-Q1: Is this Schottky-diode protection circuit appropriate?

Halil ibrahim tuncer
Prodigy 20 points
Part Number: UCC5390-Q1
Other Parts Discussed in Thread: UCC5390

Tool/software:

Hello,

While reviewing reference designs for the UCC5390-Q1 isolated gate driver, I found a circuit similar to the attached schematic. In this design, Schottky diodes are placed between VCC2, VEE, and GND2 nodes. I would like to confirm whether this configuration is suitable as a protection network (e.g., against negative transients, false turn-on, gate return currents, etc.).

Could you please clarify:

  • Is this topology appropriate for protecting the secondary side of the UCC5390-Q1? In which scenarios is it recommended or not recommended?

  • Are the diode placements and current directions correct? Would you suggest a TVS diode or another protection approach instead?

  • For diode selection (e.g., B240A-13-F), what criteria should be used regarding reverse voltage, current rating, leakage, and recovery?

  • Does this network affect power-up/power-down sequencing or negative VGS limits (benefits or risks)?

  • Is this configuration explicitly recommended in the datasheet or application notes? If so, could you point me to the relevant section/figure?

Thank you in advance for your support.

  • 0
    TI__Mastermind 23176 points

    Hi Halil,

    The UCC5390 has internal ESD diodes between OUT and the two supply rails, as well as across the supply itself. However, external diodes can handle more current, and they will prevent the UCC5390 from being damaged in very noisy conditions. 

    I don't understand your net labels, but here is an ESD diode protection circuit that you can use to protect our UCC5390 from EOS:

    The gate is the most likely source of high dV/dt noise. OUT is usually shorted to either VCC2 with 11 ohms or VEE2 with 0.4 ohms, so a TVS diode across the supply will also protect the OUT pull-up network and pull-down network from EOS.

    Best regards,

    Sean