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TPS3760: Is there a way to keep Reset output low at startup?

Matthew Coolidge
Prodigy 40 points
Part Number: TPS3760


Tool/software:

I'm using the TPS3760 to monitor for under-voltage conditions, specifically at startup. In my circuit during power-up, RESET is pulled high for about 1 second before going low until the UV sense condition is met. 

Is there a way to hold RESET low at startup? I've tried different capacitances on CTR, but no change is observed.

In the screen capture below, CH2 is VDD, CH3 is RESET output, and CH4 is the voltage from which SENSE is monitored.

Is this behavior expected?

Thanks,

Matt

  • 0
    TI__Genius 10110 points

    Hi Matt, Thanks for you question!

    Could you please share your schematic and clarify what OPN you are using? 

    Best,

    Sila

  • 0 in reply to Sila Atalar
    Prodigy 40 points

    Hi, thank you for the quick response. I'm using part TPS3760A012DYYR

    Here is a snippet of my schematic:

    TPS3760 VDD is 48V

  • 0 in reply to Matthew Coolidge
    TI__Genius 10110 points

    Hi Matt, 

    Thanks for the schematic. 

    What is your power up sequence? Are you powering 48V rail first, and 1 second later VDD? That explains why we are seeing RESET is being pulled high. In that case, since the device has not power, the RESET will be high.

    If you powering VDD first, I will need more information. Please probe CTS and CTR voltages at the beginning (with SENSE and RESET). And one recommendation is remove CTS cap, and try with different CTR values. 

    Hope this helps! 

    Best,

    Sila 

  • 0 in reply to Sila Atalar
    TI__Genius 10110 points

    Also, I would like to quickly highlight we do have a 48V supervisor that can handle voltages up to 105V at VDD, SENSE, and RESET pin. 

    TPS37100 is a new device, and if you are interested with the industrial grade, please let me know. 

    Thanks,

    Sila

  • 0 in reply to Sila Atalar
    Prodigy 40 points

    Hi Sila, 

    Thanks. The VDD pin of the TPS37660 is powered by 48V at turn on (oscope trace shown in white).

    You make a good point about the power sequence. The power to the output buffer is 5V, and I believe that is in sync with the 48V, but I'll double check. 

    I did make a point to probe the actual RST pin and not just the buffered output, but I'll review my results to be sure.

    Thanks,

    Matt

  • 0 in reply to Matthew Coolidge
    Prodigy 40 points

    Just to confirm, is the RST pin expected to stay low at startup? 

  • 0 in reply to Matthew Coolidge
    TI__Genius 10110 points

    Hi Matthew, 

    Yes, in startup, if VDD< VDD(min) or SENSE < Vith, the RESET should be low.

    Please find the device functionals mode in below. Depending on the VDD and SENSE voltage, and MR, which is Manual RESET input, the RESET will react differently. 

    Thanks for checking the behavior at RESET pin. I will close the thread for right now. But please feel free to open by respond here once you have more bench data or would like to review the result. 

    Best,

    Sila