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TPS4813-Q1: Behavior of VGS comparator after MAIN FETs fully turn on?

Michelle Mathew
Prodigy 190 points
Part Number: TPS4813-Q1

Tool/software:

Hello,

I’m planning to use the TPS4813-Q1 in a high-side synchronous switch topology with bypass FETs (G2) and main FETs (G1). I understand the device has VGS comparators for both G2 and G1 and that it checks VGS during the transition from bypass to main to ensure V_G1_GOOD = 7 V is reached before handing over.

My question: once the MAIN FETs are fully conducting (active mode), does the TPS4813 continue to monitor G1 VGS? If the MAIN FETs’ VGS falls below 7 V during steady operation, will the TPS4813:
• generate a fault or warning, or
• actively turn OFF the MAIN FETs, or
• leave the MAIN FETs conducting (no action)?

If this is documented, please point me to the datasheet/technical notes. If not, what’s the recommended way to detect/handle a sagging MAIN-FET VGS during active mode?

  • +1
    TI__Expert 7821 points

    Hi Michelle, 

    Before the V(G1_GOOD)/V(G2_GOOD) threshold has been met, the device will not monitor the SCP comparator output so short circuit protection will not be available during that time period. However, there will be no fault warning or action taken by the device. The gate can be pulled low due to a charge pump UVLO, input UVLO, or short circuit faults. Gate to source would have to be monitored but assuming that the right steps are taken for proper functionality (input capacitance, properly sizing BST, inrush control), VGS should not dip. 

    Thanks,

    Rishika Patel