LM5066: No Load Power

A design issue could contribute if:

• The VDD pin is overloaded (e.g., used to pull up too many external signals like ADR0–ADR2, PGD, or SMBus pins without current-limiting resistors, drawing >30 mA and triggering the internal current limit).
• The bypass capacitor on VDD is absent, incorrect (e.g., not ceramic or too small), or poorly placed, causing instability.
• UVLO/EN or OVLO pins are misconfigured (e.g., UVLO/EN grounded, disabling the device), preventing proper startup, though this typically wouldn't drop VDD to 0.21 V.
• High-frequency transients on VIN (e.g., from your PCB's power source) are disrupting the regulator—add a TVS diode (e.g., 5.0SMDJ60A) at VIN if not present.

The low GATE (1.2 V instead of ~VIN + 12 V, or ~40 V total) and OUT (1.1 V instead of 28 V) are likely downstream effects of the low VDD, as it powers internal logic and the charge pump for GATE drive. If VDD fails to reach its POR threshold (~4.1 V), the device won't enable properly, keeping GATE low and the external MOSFET off (hence low OUT).   

• Verify the 1 μF ceramic bypass cap is present and connected directly to VDD and GND with short traces.
• Check current draw on VDD (disconnect external loads if any) and ensure VIN is stable (no sags below 10 V)

1. Check VDD-GND Traces:
   • Measure trace length from VDD pin to 1 µF cap and GND. Keep <1 cm with low inductance (wide traces or vias to ground plane). Inspect for solder bridges with a magnifying glass.
   • Test resistance between VDD and GND (should be >1 MΩ). A low value indicates a short.
2. Verify VDD Loading:
   • Disconnect external connections to VDD (e.g., pull-ups for ADR0–ADR2, PGD, SMBus). Measure VDD current with a multimeter; should be <1 mA with no load.
   • If pull-ups are used, ensure resistors are >10 kΩ to limit current.
3. Check UVLO/OVLO Configuration:
   • Verify UVLO and OVLO resistor dividers (pins 6 and 7). For 28 V VIN, UVLO should be set below 28 V (e.g., default ~8.2 V or adjust via resistors per datasheet: V_UVLO = 1.25 V × (R1 + R2)/R2). OVLO should be above 28 V (e.g., default ~100 V).
   • If UVLO is grounded or OVLO is too low, the device won’t enable. Measure pin voltages with a multimeter.
4. Assess VIN Transients:
   • Use an oscilloscope to monitor VIN for high-frequency noise (>100 kHz) or fast transients (<1 µs rise). Look for dips below 10 V or spikes approaching 40 V (TVS clamp level).
   • Add a 10 µF ceramic cap or ferrite bead (e.g., BLM21PG221SN1) in series with VIN if noise is present. Ensure the 0.1 µF cap is close to the VIN pin (<1 cm).
5. Test for Chip/Installation Issues:
   • Replace the LM5066 with a new chip, following ESD precautions (e.g., grounded wrist strap). Retest VDD, GATE, and OUT voltages.
   • If VDD remains low, use a hot air rework station to reflow or replace the chip, ensuring clean soldering.
6. Monitor Faults:
   • Check the FAULT pin (low indicates fault) and read SMBus status registers (if used) to identify overcurrent, thermal, or UVLO faults.

Conclusion

The low VDD (0.21 V) is likely due to a short (solder issue), defective chip, or excessive VDD loading, with VIN transients or UVLO/OVLO misconfiguration as secondary possibilities. Problematic VIN frequencies are >100 kHz or fast transients (<1 µs). Start by checking VDD-GND traces and resistance, then verify loading and UVLO/OVLO settings. If unresolved, replace the chip