Tool/software:
Hi,
Could you provide guidance on layouts where we use only ceramic capacitors as suggested in figure 7-11 of the datasheet ?
Layout from figure 7-12 only suggest a "standard" layout with 2 feedback resistors.
Best regards
Tool/software:
Hi,
Could you provide guidance on layouts where we use only ceramic capacitors as suggested in figure 7-11 of the datasheet ?
Layout from figure 7-12 only suggest a "standard" layout with 2 feedback resistors.
Best regards
Hello,
The layout will be almost the same.
Just make sure that the additional Vsns components are close to the IC similar to the resistor divider shown in the example.
Best regards,
Ridge
Hello,
Are you able to post a regular jpeg or png file to this post for us to review?
Best regards,
Ridge
Hello,
The Vsense components should be placed right as close to the Vsense pin as possible.
You would then route a trace from the Vsense network to the output of the device.
The example shown has the components too far from the IC.
Please refer to the layout guideline in the datasheet. This image only has feedback resistors, but the placement represents how you should try to orient the additional Vsense components.
Best regards,
Ridge
Hi, so something like this should be better
feedback resistors close to vSense and extra components placed better