Tool/software:
Hello TI engineers and people on board this awesome knowledge forum!
I'm Martin a hardware developer from Spain that helps in https://github.com/vroland/epdiy-hardware epdiy project that is an open source parallel Eink controller (Using Espressif S3 MCU as core driver)
Recently some users have tried Eink Carta 1300 displays that seem to have a different power-up sequence that the TPS65185 standard:
ED103MC1 is the display I'm testing with. (With older display non Carta 1300 everything works. )
Power Rails must be sequenced in the following order
- VSS → VDD → VNEG → VPOS (Source driver) → VCOM
- VSS → VDD → VGL → VGH (Gate driver)
In order to achieve that I've read the relevant part in the datasheet and also asked the articial inteligence that was not intelligent enough to give a proper answer.
PSEUDO CODE Tested:
void tps_set_power_seq(i2c_port_t i2c_num, uint8_t seq) {
tps_write_register(i2c_num, TPS_REG_UPSEQ0, 0x9c); // NOT CHANGE 0x9C
tps_write_register(i2c_num, TPS_REG_ENABLE, 0x00); // Standby
vTaskDelay(pdMS_TO_TICKS(10));
tps_write_register(i2c_num, TPS_REG_ENABLE, 0x01); // Active
}
My question is:
After changing the UPSEQ 0x09 register is there any other step to do to "activate" this new power sequence?
Running that code trying to make a different power sequence I get in the logs:
INT1 (0x07): 0x00
INT2 (0x08): 0x02
VNEG_UV: VNEG undervoltage
VADJ (0x02): 0x03
VPOS/VNEG: ±15.000V
VCOM1 (0x03): 0xA0
VCOM2 (0x04): 0x00
VCOM voltage: -1.60V
ACQ bit: CLEAR
PROG bit: CLEAR
HiZ bit: CLEAR
AVG: 1x measurements
TMST_VALUE (0x00): 0x00
Temperature: 0°C
TMST1 (0x0D): 0x20
READ_THERM: IDLE
CONV_END: DONE
DT threshold: 2°C
TMST2 (0x0E): 0x78
COLD threshold: 0°C
HOT threshold: 50°C
UPSEQ0 (0x09): 0xE4
VDDH_UP: STROBE4
VPOS_UP: STROBE3
VEE_UP: STROBE2
VNEG_UP: STROBE1
So I'm actually not changing any STROBE order that is the default that works with most Eink displays.
Can you please tell me if I'm forgetting to do something obvious?
Many thanks in advance