TPS65185: How to properly set up a new power up sequence and activate it

Martin Fasani

Part Number: TPS65185

Tool/software:

Hello TI engineers and people on board this awesome knowledge forum!

I'm Martin a hardware developer from Spain that helps in https://github.com/vroland/epdiy-hardware epdiy project that is an open source parallel Eink controller (Using Espressif S3 MCU as core driver)

Recently some users have tried Eink Carta 1300 displays that seem to have a different power-up sequence that the TPS65185 standard:

ED103MC1 is the display I'm testing with. (With older display non Carta 1300 everything works. )
Power Rails must be sequenced in the following order

VSS → VDD → VNEG → VPOS (Source driver) → VCOM
VSS → VDD → VGL → VGH (Gate driver)

In order to achieve that I've read the relevant part in the datasheet and also asked the articial inteligence that was not intelligent enough to give a proper answer.

PSEUDO CODE Tested:

void tps_set_power_seq(i2c_port_t i2c_num, uint8_t seq) {

 tps_write_register(i2c_num, TPS_REG_UPSEQ0, 0x9c); // NOT CHANGE 0x9C

 tps_write_register(i2c_num, TPS_REG_ENABLE, 0x00); // Standby

 vTaskDelay(pdMS_TO_TICKS(10));

 tps_write_register(i2c_num, TPS_REG_ENABLE, 0x01); // Active

}

My question is:
After changing the UPSEQ 0x09 register is there any other step to do to "activate" this new power sequence?

Running that code trying to make a different power sequence I get in the logs:

INT1 (0x07): 0x00
INT2 (0x08): 0x02
VNEG_UV: VNEG undervoltage
VADJ (0x02): 0x03
VPOS/VNEG: ±15.000V
VCOM1 (0x03): 0xA0
VCOM2 (0x04): 0x00
VCOM voltage: -1.60V
ACQ bit: CLEAR
PROG bit: CLEAR
HiZ bit: CLEAR
AVG: 1x measurements
TMST_VALUE (0x00): 0x00
Temperature: 0°C
TMST1 (0x0D): 0x20
READ_THERM: IDLE
CONV_END: DONE
DT threshold: 2°C
TMST2 (0x0E): 0x78
COLD threshold: 0°C
HOT threshold: 50°C
UPSEQ0 (0x09): 0xE4
VDDH_UP: STROBE4
VPOS_UP: STROBE3
VEE_UP: STROBE2
VNEG_UP: STROBE1

So I'm actually not changing any STROBE order that is the default that works with most Eink displays.

Can you please tell me if I'm forgetting to do something obvious?
Many thanks in advance

26 days ago

0 Sarah Lao 26 days ago

TI__Genius 9927 points

Hi Martin,

Thanks for reaching out on E2E!

For UPSEQ0 to be written properly, the device should be in Standby mode before the write.
(Wakeup pin HIGH, while PWRUP pin is low)

And to set the device into active mode, specifically bit 7 of the ENABLE register needs to be set to '1', i.e. a value of 0x80 (1000 0000) should be written to TPS_REG_ENABLE

To debug, could you try:

Setting the device in standby mode by setting WAKEUP pin HIGH ,and keeping PWRUP pin LOW
Write 0x9C to UPSEQ0
Do an immediate readback/log of UPSEQ0 to check if 0x9C was written properly
Set device to Active mode by either writing 0x80 to ENABLE register, or pulling PWRUP pin HIGH
Check UPSEQ0 and strobe sequence.

Let me know if you have any trouble with the above steps.

Best Regards,
Sarah

0 Martin Fasani 26 days ago in reply to Sarah Lao

Prodigy 10 points

Hello Sarah,

many thanks for your answer. I was getting the wrong I2C commands that's my bad. I tried what you recommend in my code:

void tps_set_power_seq(i2c_port_t i2c_num, uint8_t seq) {
    tps_write_register(i2c_num, TPS_REG_ENABLE, 0x40); // Standby mode
    // WAKE UP mode for PMIC
    ESP_ERROR_CHECK(pca9555_set_value(I2C_NUM_0, (PCA_PIN_PC15 >> 8), 1)); // WAKE up
    ESP_ERROR_CHECK(pca9555_set_value(I2C_NUM_0, (PCA_PIN_PC13 >> 8), 0)); // PWR down
    vTaskDelay(1);
    
    // power up order
    tps_write_register(i2c_num, TPS_REG_UPSEQ1, 0x56);
    tps_write_register(i2c_num, TPS_REG_UPSEQ0, seq);  // does NOT CHANGE to 0x9C
    printf("Setting TPS_REG_UPSEQ0 to %x\n",seq);
    
    tps_write_register(i2c_num, TPS_REG_VADJ, 0x04);   // CHANGES!
    //tps_write_register(i2c_num, TPS_REG_ENABLE, 0x40); // Standby mode
    tps_write_register(i2c_num, TPS_REG_ENABLE, 0x80); // Active
}

But sadly I still cannot make it work.
In my PCB the WAKEUP and PWRUP signals are connected via an IO expander that is why it looks that way. I can change successfully other config paramenters like:

TPS_REG_VADJ to 0x04. And it does change correctly. But the UPSEQ0 and 1 still resist. No matter what I do they seem to have the same value. Tomorrow will try again. Many thanks for your help!

+1 Sarah Lao 25 days ago in reply to Martin Fasani

TI__Genius 9927 points

Hi Martin,

Thanks for the update! Do you have any other updates on how this is working now?

It is strange that you are able to write to other registers like VADJ, but not the UPSEQ registers...
Out of curiosity, are the DOWNSEQ registers able to be written to?

I will say, I think the
PWRUP should be low before WAKEUP is pulled high,
and then Standby bit (0x40 to ENABLE) would only need to be set if the device is already in ACTIVE mode prior to your code snippet.

Best Regards,
Sarah

0 Martin Fasani 24 days ago in reply to Sarah Lao

Prodigy 10 points

Thanks Sarah!

> I think the PWRUP should be low before WAKEUP is pulled high,

This is actually the key solution. And I also cleanup from any other initiallization any power off / power on that touches TPS PMIC leaving as first command the update function.
Sadly even if I can control power up sequence now this Carta 1300 display still doesn't work, is the first that does not work, if you check https://github.com/vroland/epdiy there is a list of over 20 display panels (Different resolution and bit-widths) and all work perfectly fine with TPS65185.

What recommendations would you give to start looking into, when TPS65185 reports VNEG undervoltage ?
Since in other same size displays works perfectly, what would be different in this particular Carta 1300, that it cannot stabilize the line ?
FACT is: Waveshare has a 10.3 ITE8951 controller that also uses same PMIC, a friend tried it with that upon my request, and seems to work correctly. Can it be that there is an error in our design for this specific panel?

In this schematic you can see how is the latest implementation of TI PMIC:

https://vroland.github.io/epdiy-hardware/build/boards/epdiy-v7_schematic.pdf

Thanks a lot for your great feedback. Now I fully understand how this works!

0 Ishtiaque Panhwar 22 days ago in reply to Martin Fasani

TI__Genius 16950 points

Hi Martin,

Due to national holiday in US, most of the experts are out of office today. Please expect delay in response. Thanks for your patience!

Regards,

Ishtiaque

0 Sarah Lao 20 days ago in reply to Martin Fasani

TI__Genius 9927 points

Hi Martin,

Glad the power up sequence is fixed.

Is VNEG UV the only register reporting an interrupt? And are you able to physically measure what value this is?

I'm not seeing any issues with the VNEG connections in the schematic, are you able to compare the layout of the panels?

This thread may also be relevant: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1074320/tps65185-power-up-troubleshooting?tisearch=e2e-sitesearch&keymatch=tps65185%252525252525252520vneg#

Best Regards,
Sarah

0 Martin Fasani 20 days ago in reply to Sarah Lao

Prodigy 10 points

Hi Sarah,

> Is VNEG UV the only register reporting an interrupt? And are you able to physically measure what value this is?

Yes so far is the only one returning VNEG undervoltage. But as is the first one, failing to regulate this, just stops the whole power-up sequence. At least without an oscilloscope or precise measurement tools this is impossible to measure because it fails to reach stable -15 VOLT.
Layout of the two 10.3 panels, ED103TC2 and ED103MC1 look exactly the same and the datasheet does not give any hints that there is a different VNEG setting. A bit lost with it. My partner sent two boards to EINK to see if they can figure out what it is.

Thanks a lot for all your help

0 Sarah Lao 19 days ago in reply to Martin Fasani

TI__Genius 9927 points

Hi Martin,

Thanks for the update. Please do update if you have any new discoveries.

Best Regards,
Sarah

0 Martin Fasani 15 days ago in reply to Sarah Lao

Prodigy 10 points

I did a last check comparing Waveshare 10.3 control board (It works) using same TPS65185.
Basically circuit is the same. It just has different inductors (Same uH value, slightly different resistance mark)
And has some additional "filtering capacitors" in the VDD lines:

VIN

22uF+10uF

47uF+47uF+10uF (Waveshare)

VIN_P

22uF+10uF (our controller)

47uF+47uF+10uF(Waveshare)

VN_SW

L1 4.7uH

L6 GSDR43-4R7M +

VEE_IN

4,7uF

4,7uF+4,7uF

VEE_D

C27 2,2uF

C46 4.7uF

VDDH_D

C33 2,2uF

C18 4.7uF

VB_SW

L2 2.2uH

L3 GSDR32-2R2M

I could try switching the TPS Circuit to something similar but I highly doubt that this can be the culprit of VNEG undervoltage.

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TPS65185: How to properly set up a new power up sequence and activate it