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TPS388C0-Q1: MONx Protection, Latching Output and Watchdog Reset

Tilo Lutz
Prodigy 10 points
Part Number: TPS388C0-Q1
Other Parts Discussed in Thread: TPS3762-Q1, TPS37100-Q1, TPS3760-Q1, TPS3700

Tool/software:

Hi

I have some questions which I was not able to answer with the datasheet.

In the datasheet, there is a latched WDO mentioned in context with WDO_DLY. How is it possible to configure a latched WDO? In our setup, WDO should be latching and stay low when the watchdog triggered.

There seems to be a mistake in the datasheet. In 7.5.1.2, register VMON_CTL, FORCE_WDO_LOW is using bit4 to bit7 but later, bit5 to bit7 are defined as reserved. Is one of the additional bits used for the latching option?

What happens when WDE changes from high->low. Will this disable the watchdog and deassert WDO? Will a following low->high restart the watchdog? Would this be comparable to write a 1 into WDT_ERROR?

There seems to be a typo in the datasheet:

"both NRST and NRST" seems to be wrong, I assume "NRST and NIRQ" is meant.

For the MONx pins, there is a maximum voltage specified. What happens, when in case of a defect of a voltage regulator, the voltage at MONx is higher? Are there clamping diodes?
Is it allowed to insert a series resistor to limit the current into the pin? When yes, what is the maximum allowed current into the pin? What type of circuit do you recommend for OV protection?

Thank you very much.

  • 0
    TI__Genius 9820 points

    Hi Tilo, 

    1. Watchdog latch option is only configurable in OTP (One time programmable).
    2. I will check with my team and understand which one needs to be updated. Either Table 7-23. BANK1 Registers or Table 7-25. VMON_CTL Register Field Descriptions might need be fixed. 
    3. When the WDE pin is low to disable the watchdog timer, changes on the pin is responded to immediately. When the watchdog goes from disabled to enabled, there is a startup delay and close and open window sequence.
    4. Thanks for pointing out the typo in the explanation section of the Figure 7-14. In the next revision, we can fix that one. 
    5. The recommended maximum voltage for the VMON pins 5.5V.  I don't think we do have any clamping but I need to get the confirmation. I will get back to you on this once I got a clarification.
    6. According to datasheet,  Input current MONx pins, Imonx =20 uA (max)

    Can you please clarify how many Vmon channel you will need and what voltages are you planning to monitor? 

    Best,

    Sila

  • 0 in reply to Sila Atalar
    Prodigy 10 points

    Hello Sila

    Thank you for your quick response.
    1. Will it be possible to get customer-dependend OTP values in future?
    3. When the timer gets disabled, will this also reset WDO state? That's not clear for me yet.
    6. I'm not sure how this is meant. At the moment, I understand this as a maximum current when active. So when I add a 1k series resistor for protection, because of the input current it will cause a voltage drop up to 20mV and therefore, a reading error.

    I plan to monitor several voltages (around 14 to 16) between 500mV and 19V. The monitor function must still work in case a monitored voltage regulator is defective and its output voltage is too high. When it's about regulators in the design, the monitor-circuit can turn them off. But this is delayed and for a short time, voltage on MONx might be higher than 5.5V. I also have to monitor external voltages up to 30V in failure cases which can't get turned off so I have to assume those failure case as something that might be permanent.

    My actual plan is to place a protection circuit with a high resistive voltage divider and an op-amp. I would like to avoid that because of space limitations.

    Best regards,

    Tilo

  • 0 in reply to Tilo Lutz
    TI__Genius 9820 points

    Hi Tilo, 

    Thanks for sharing more details. I want to let you know that we do have supervisor that can monitor 30V. Please check TPS3760-Q1, TPS3762-Q1 ( Functional safety Rated), depending on the maximum transient you are expecting you can also check TPS37100-Q1. This way you don't need the discrete monitoring. Please let me know if you'd like to discuss on any of the supervisor I highlighted. We can work together to understand which one could be the best fit. 

    When the watchdog is disabled, the WDO output is expected to be high. 

    You need to have appropriate the resistor divider at the VMON pins. While you picking the resistor values you need to consider the voltage monitoring window ( OV assert & UV assert). Once you have the resistor divider, there is no additional series resistor need  for Vmon to limit the current. 

    I will be reaching out to you to understand you OPN needs. We need to align on your customer depended OPN. I will be sending an email to understand your project detail such as volume, timeline, and supervisor/watchdog requirement. 

    Best,

    Sila 

  • 0 in reply to Sila Atalar
    Prodigy 10 points

    Hello Sila

    Thank you for your proposals.  We have very, very little space and 14-16 voltages to monitor. The required space sums up. We don't have enough space for s single integrated circuit.
    I started with a complete discrete approach by using a TPS3700 in WSON housing. That's already too big. We also need a possibility to do a full self-test during run-time. a BIST is not enough. My idea with the TPS38x family is to change UV and OV levels for a single channel to cause a reaction. That's very nice as it saves space for additional components.

    I'm looking forward to get your email.

    Best regards,

    Tilo

  • 0 in reply to Tilo Lutz
    TI__Genius 9820 points

    Hi Tilo, 

    Just send you an email. Please let me know if you did not receive it.

    Thanks!

    Sila