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BQ79616-Q1: Problems with sampling values ​​when using BQ79616 in supercapacitor scenarios

?? ?
Prodigy 30 points
Part Number: BQ79616-Q1
Other Parts Discussed in Thread: BQ79616

Tool/software:

Hello, I am trying to use the BQ79616 in a supercapacitor scenario.I have 2 questions.

(1) After using an external independent power supply, we found that when the supercapacitor voltage is close to 0V or very low, the value fed back by the BQ79616 jumps, especially the third channel, which always shows a unique value. What is the reason for this? Do the sampling values ​​of the BQ79616 fluctuate at low voltages?What should I do to ensure that the sampling values ​​of all voltage channels are accurate at 0V?

(2) When no external power supply is used, the BQ79616 loses power due to instantaneous discharge of overcapacitance. After recharging and restarting, the BQ9616 will have abnormal power rails such as TSREF and report a fault  TSREF_OSC & TSREF_UV .How do I solve this problem? Is there any way to reset BQ79616 under abnormal circumstances?

  • 0
    TI__Expert 7000 points

    1. The BQ79616 cannot sample accurately with an input of 0V. 
    Its only accurate with a cell voltage between 1-5V.

    Look at the accuracy specification in the EC table of the datasheet.

    2. For this you will have to take a closer look at our references, like LDOIN, TSREF, REFCAP etc... When you are not supplying sufficient power to LDOIN, then you can have downstream effects on TSREF. When TSREF is not properly supplied, then you will have OSC and UV events occur. 

    Best,

         Quentin

  • 0 in reply to Quentin Silic
    Prodigy 30 points

    I don't see the range clearly in datasheet. Can you help point it out? However, the manual states in the accuracy section that the cell voltage can reach 0V.

    For 2，I mean If LDOIN loses voltage and then meets the supply voltage again, TSREF will appear and a fault will be reported. Can this be reset by software?

  • 0 in reply to ?? ?
    TI__Prodigy 110 points

    1) Can you help explain your architecture and where the supercapacitors are located?

    2) To verify the accuracy of the cells, can you measure the voltage directly at the pin node differentially in respect to the VC channel below it? Ideally, the voltage is stable enough that it can be compared at the same moment as the ADC reading. This will help identify how far off the ADC value is from the voltage reaching the pin.

    3) Most faults are latched conditions and can be cleared in SW by sending a "1" to the targeted bit within the FAULT_RST registers. If the fault cannot be cleared afterwards, then the fault is possible still present. In this case, you want to send a 0x1 [RST_PWR] to the register 0x331 [FAULT_RST1].

    Thanks,
    Esteban