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LP87524J-Q1: Question about timing diagram

Chase Jeong
Mastermind 7425 points
Part Number: LP87524J-Q1
Other Parts Discussed in Thread: AWR1843AOPEVM

Tool/software:

Dear TI experts,

My customer tests LP87524J-Q1 in their own PCB.

1. In this process they want to check functional block diagram (which is more specific than page 15 of datasheet) and timing diagram which includes reset and en signal.

Could you check it?

Best regards,

Chase

  • 0
    TI__Genius 16540 points

    Hi Chase, 

    Functional block diagram presented in the datasheet is the one I would refer but we do not have any other. From the timing diagram, did you mean device power up and down sequence timing and related settings then those can be looked into the Technical Reference Manual (TRM); Link

    Regards,

    Ishtiaque  

  • 0 in reply to Ishtiaque Panhwar
    Mastermind 7425 points

    Dear Ishtiaque,

    Thank you for your support.

    I checked technical reference manual which you linked. But I cannot find the timing of NRST(reset) signal.

    Could you check it more?

    Or NRST pin timing is not important for operating?

    Best regards,

    Chase 

  • 0 in reply to Chase Jeong
    TI__Genius 16540 points

    Hi Chase,

    NRST is the Digital input (D/I) signal. Reset to the device. So why this would be included in the PMIC start up sequence. 

    Regards,

    Ishtiaque 

  • 0 in reply to Ishtiaque Panhwar
    Mastermind 7425 points

    Dear Ishtiaque,

    Thank you for your support.

    My customer did some more test.

    1. What is the default setting of EN1, EN2, EN3 pins without I2C connection?

    For now, the device is working only EN1 is high. (with other combinations-only EN2 high, only EN3 high, EN1,EN2 hign,....-device does not working.)

    2. In the schematic of AWR1843AOPEVM, I can see that ENx pins are pulled up. Is it necessary if I2C is not connected?

    Please check this issue. Thanks.

    Best regards,

    Chase

  • 0 in reply to Chase Jeong
    TI__Genius 16540 points

    Hi chase,

    In LP87524J-Q1, the EN1 is configured as ENABLE signal for power up and down sequences of all buck regulators and GPIO2 and 3. 

    Where as the EN2/GPIO2 and EN3/GPIO3 are both configured as GPO output signals and they are also enabled by EN1 with start up delay sequence and other settings shown in the TRM below.  

    Regards,

    Ishtiaque