BQ76952: BG76952 : Precharge control PDSG pin

One thing I forget to write.

According to this paragraph in the document Frequently_asked_question_BQ76952.pdf :

I should get a voltage on PCHG/PDSG of BAT_pin - 8.4V, which in my case is 12V-8.4V. However, the voltage I get is VC16 (35V) - 8.4V = 28V. 

Is possible for you to provide a schematic to help clarify your system configuration?
For instance I am confused how your pin VC16  = 35V, but your BAT_pin = 12V? 
BAT and VC16 should be at a similar voltage, separated by a diode + series Resistor on the BAT pin and a RC filter on the VC16 side.

I want to clarify the intended purpose of the PCHG/PDSG pins:

The Precharge pin can be used to reduce the charging current for an undervoltage battery by charging using a high-side PCHG PFET (driven from the PCHG pin) with series resistor until the battery reaches a programmable voltage level. When the minimum cell voltage is less than a programmable threshold, the PCHG FET will be used for charging.

The Predischarge pin can be used to reduce inrush current when the load is initially powered, by first enabling a high-side PDSG PFET (driven from the PDSG pin) with series resistor, which enables the load to slowly charge. If PREDISCHARGE mode is enabled, whenever the DSG FET is turned on to power the load, the device will first enable the PDSG FET, then transition to turn on the DSG FET and turn off the PDSG FET.

If this is your intended purpose with those pins then please let me know, and we can move forward debugging their configuration.

But when you say "I use the PDSG pin to control a optocoupler to enable the precharge. I need 3,3V on the PDSG pin when he's active." It sounds like you would rather have logic output that follows the pin status of the CHG/DSG pins. If that is the case I would recommend configuring the DCHG/DDSG pins for this purpose instead.

When the DCHG/DSG pins are configured for DDSG and DCHG functionality, they provide signals related to protection faults that (on the DCHG pin) would normally cause the CHG driver to be disabled, or (on the DDSG pin) would normally cause the DSG driver to be disabled. These signals can be used to control external protection circuitry, if the integrated high-side NFET drivers will not be used in the system. They can also be used as interrupts in manual FET control mode for the host processor to decide whether to disable the FETs through commands or using the CFETOFF and DFETOFF pins.

Hi Gavin Long,

Thanks for your reply, I will try to clarify my configuration and my question.

1 - Here the schematic of my test board (custom), BQ76952 below : 

As you can see : 

- I have 12V coming from a DC/DC 36V -> 12V that goes to the BAT pin. 

- On HV0/VC16 I put 36V at the input

Is this way of supply incorrect? If yes is there a diagram I could refer to?

2 - About the intended purpose of the PCHG and PDSG pin : 

That's exactly how I expect it to work. Particularly on the PDSG pin, which is what interests me in this question. 

3 - How I planned to use PDSG (probaly false)

I thought that the PDSG pin, when active, would have an output of 3.3V. So, i nstead of a P-MOSFET, I was thinking of using a TLP3546A optocoupler like the schematic below.

However, it seems that this is incorrect? The output on PCHG/PDSG pin when active is HV - 8.4V? In my case, that's 36V-8.4V = 27.6V. Please correct me if I'm wrong.

I hope this message clarifies any points that were unclear. If anything is still unclear, please let me know. Thank you again for your help.

Brice 

One additional thing about how PDSG is expected to work. I definitely want to use this pin because I need the Settings:FET:Predischarge Timeout and Settings:FET:Predischarge Stop Delta functions. These seem to work when I look at the changes in the FET status register described in my first message. 

Here is the EVM Reference Design: https://www.ti.com/lit/df/tidm788/tidm788.pdf?ts=1756999257378

The BAT pin is used for the CP1/CHG/DSG pins to dictate the voltage level of those outputs. For instance when enabled CHG = CP1 = BAT+11V, when disabled CHG=BAT. This is because the source of the CHG FET is should be BAT (top of battery stack). When you have a fixed 12V at BAT_pin, but the CHG/DSG FETs are seeing 36V, they will not be correctly overdriven to 36V + 11V= 47V (if using NFETs), as they should be. Instead they are outputting 23V = 12V+11V, which is incorrect when the sources are at 36V.

The PDSG/PCHG driver is design to driver a PFET device and  operates by pulling the pin voltage slightly lower to enable the PFET. Therefore the active voltage level is 8.4V below whichever is higher (BAT vs LD pin). Since it does not require the Charge-Pump it uses a diode OR for the highest voltage. When in-active (disabled) the PCHG/PDSG pins are Hi-Z and therefore floating. If there is no pull-up resistor on the pin, this may explain why you are seeing ~1.3V when disabled, which is likely where the leakage between the PDSG pin and the optocoupler equalize.

The PDSG pin cannot be programmed to output 3.3V, it will always be MAX(BAT,LD) - 8.4V when enabled, or floating when disabled.
However the DDSG/DCHG pins can be programmed to a specific IO voltage (1.8V, 3.3V, or 5V). Although they do not include the Predischarge Timeout and Predischarge Stop Delta Settings you are interested in. They instead will follow the same logic as CHG/DSG pins.