• State Resolved
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 45 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TPS2492: Power good behavior

Ben
Intellectual 400 points
Part Number: TPS2492

Tool/software:

Hi TI team,

I designed back-to-back FETs using the TPS2492 IC and have a question about the PG behavior. (back to back is common source)

If the first FET develops a short fault, the input voltage appears at the output through the body diode of the second FET, even when the TPS2492 has not been enabled.

At this time, the TPS2492 keeps the PG pin low even though the enable signal is not present.

Is this the correct PG behavior as intended?

Thank you.

  • +1
    TI__Mastermind 39780 points

    Thanks for reaching out. This is an expected behaviour. As the VDS is close to zero, PG pin will low although the device is not enabled. PG goes low after VDS of MOSFET has fallen to about 1.25 V and a 9-ms deglitch time period has elapsed.