Tool/software:
Hi TI team,
I designed back-to-back FETs using the TPS2492 IC and have a question about the PG behavior. (back to back is common source)
If the first FET develops a short fault, the input voltage appears at the output through the body diode of the second FET, even when the TPS2492 has not been enabled.
At this time, the TPS2492 keeps the PG pin low even though the enable signal is not present.
Is this the correct PG behavior as intended?
Thank you.