Tool/software:
Hi,
We have an existing design using the LM5156 and unfortunately we are having to try and augment the design with a high speed over current comparator. If shorts occur at the output of a boost converter configuration we are finding the primary power switching FET often gets destroyed as the output current saturates the primary inductor allowing the FET to switch very high currents.
From my understanding of the LM5156, even current sense can not overcome this state as the timing is way to fast and minimum on-time still has to be honoured before CS cycle termination can switch the FET off.
To this end, we are attempting to disable the LM5156 using its UVLO/EN pin and a latching high speed comparator. The hope is that the current through the inductor exceeds a peak level that we can detect fast enough and that this event can be detected and the EN pulled low within a few 100ns. perhaps 2-3 switching cycle @ 500Khz.
The rest of the circuit is protected with a high speed fuse, but currently we blow the fuse and the FET. Our supply is a very high current capable Li-ion battery pack, currents under short circuit can be very large.
The outstanding question is can you offer specific propagation times between EN pin low and GATE low for the LM5156. The timing diagram in the datasheet is not explicit enough in my opinion, in fact the closest we see is that upon grounding EN pin there will be 2 cycles before SS is grounded. It does not explicitly state that the response to EN low is a termination of the current cycle including gate being pulled low regardless of how long the gate has been on (if it is high at the time EN falls).
Essentially you do not state the propagation delay from EN pin to the rest of the sub-systems in the IC.
It would be very useful for us in this case.
All the best
Aidan
