Tool/software:
We are preparing a design with two TPS7H3014 in series to use an 8 stage sequencer for space application.
I'm wondering, if the DOWN_N input which is controlled through an FPGA output is set LOW to start power OFF sequence, then obviously at some point the FPGA logic will be stopped and the logic output level will not be garanted to LOW anymore. In such situation, if the signal goes over the 500mV threshold, will it stop the power off sequence or once a high to low transition is detected on DOWN_N, the sequencer will apply it power OFF sequence until the end whatever the voltage logic on DOWN_N afterwards ?
In other words, can a FPGA power OFF itself through this DOWN_N pin or should this pin be driven by an externaly supplied component ?
Thank you for your support,
Best regards,
Adrien
