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LMG1020EVM-006: How to maintain the output amplitude of SN74LVC1G08 in the LMG1020EVM-006?

Makiko
Prodigy 40 points
Part Number: LMG1020EVM-006
Other Parts Discussed in Thread: SN74LVC1G08, LMG1020

Tool/software:

We use LMG1020EVM-006. This image is quoted from the EVM User's Guide: LMG1020EVM-006.We are adjusting the frequency of the function generator to achieve the narrowest possible pulse width (1 ns) at the output. 

I would like to increase the output signal amplitude of the AND gate SN74LVC1G08 used in the LMG1020EVM-006 evaluation board.
The reason is that when trying to generate narrower pulses from the SN74LVC1G08, we found that the signal amplitude decreases.

How can we maintain the output amplitude while still generating narrow pulses from the SN74LVC1G08?

  • 0
    TI__Prodigy 650 points

    Hi Makiko,

    Is the LMG1020 still being triggered by the input pulse? The driver's input high threshold is 2.6V max, which the output of the AND gate should reach that with the 5V EVM supply. Can you tell me which components you have added or removed from the board since you opened it?

    Thanks,

    Annabelle

  • 0 in reply to Annabelle Alemand
    Prodigy 40 points

    Dear Annablelle,

    Thank you for your reply! I appreciate it.

    I use LMG1020EVM-006 without any modifications. So, I input pulse into J3 on LMG1020EVM-006. The input pulse is about 100kHz or 250kHz. 

    Let me change the question. I would like to apply a higher voltage to the GaN-FET, so I want to maximize the amplitude of the output pulses from the LMG1020’s OUTL (OUTH). Based on our evaluations using the LMG1020EVM-006, it seemed that the amplitude of the signal input from the SN74LVC1G08 to the LMG1020 was proportional to the voltage at the LMG1020’s OUTL (OUTH).

    I would appreciate it if you could point out any mistakes. I would also be grateful for any advice.

    Thank you for your cooperation.

    Best regards,

    Makiko

  • 0 in reply to Makiko
    TI__Prodigy 650 points

    Hi Makiko,

    The max recommended VDD is 5.4V, so the LMG1020 output cannot be higher in amplitude than that. And yes, the amplitude of the AND gate into LMG1020 will be proportional to the voltage at the LMG1020 OUT pins. So you cannot get any higher than that to drive the FET.

    What voltage level are you wanting to drive the GaN-FETs at?

    Thanks,

    Annabelle

  • 0 in reply to Annabelle Alemand
    Prodigy 40 points

    Dear Annabelle,

    Thank you for your explanation!

    I want to drive the GaN-FET at over 4V, but as the pulse width approaches 1ns, the amplitude decreases, and currently only about 1V amplitude is being produced.

    I am also considering placing a buffer IC before the driver IC, which is after the AND gate. I am looking for a buffer IC that can operate at high speed, specifically around 1ns. Do you have any recommended products? Additionally, if you have any other suggestions, I would appreciate your advice.

    Thank you!

    Makiko

  • 0 in reply to Makiko
    TI__Prodigy 650 points

    Hi Makiko,

    Do you mean that the output of the AND gate is only reaching 1V, or the output of the driver is only reaching 1V? Because the driver only requires 1.8V for the input high threshold, and then the output of the driver will provide the 5V to the FET. 

    Another note is that when using the AND gate as a pulse shortener, the slew rate is at the maximum, so the output pulses will be rounded and not have sharp edges and is rounded at the top.

    Could you please send a scope shot of the behavior you are seeing, including the IN+ and IN- to the AND gate, the output of the AND gate, and the output of the driver? Please use tip and barrel probe method to do so if possible. 

    Thanks,

    Annabelle