TPS2373: Use the TPS2373 in a dual-signature PD system

Hi Charles,

Thanks for reaching out.

According to the system diagram you have provided, we have come up with two possible options as following:

Option 1:

Diagram: 

We assume system 1 power is supply by the buck converters connected from type C port. Only PD through required with TPS2372. System 2 will have a PSE TPS23881. A dc/dc will be needed to regulate the voltage. This will need minimum parts to do PoE PD for system 2 and PoE device. The PoE signature will still work. But the CAT cable between system 1 and system 2 cannot be too long (especially not for 100m here), since the system might fail Sifos test with long cables. The CAT cable between system 1 and system 2 will have 57V as long as PoE PD is established on TPS2372, which will be a ESD or Inrush current concern for frequent plug and unplug.

Option 2:

This is a PoE Daisy-Chaining solution which has been used before as following:

Using one PD and one PSE in each system, it will be able to do PD for each system in the chain. And it can be extended even further.

The 802.3 compliance and distances between devices will not be a concern comparing to option 1.

Please let me know if you have any questions about these two options.

Best regards,

Zhining

Thank you for helping review the design.

The customer has strict size constraints on the device-side board, so your earlier suggestion may be difficult to implement.

We need to provide feedback to the customer, and we have two questions:

1. Is the customer’s proposed design technically feasible?
2. Can it support automatic detection and classification?

Additionally, if we only want to use a PoE adapter to supply power to the device—without automatic detection/classification—and minimize both component count and size, do you have any suggestions?

Thanks in advance, and we would also appreciate any guidance on trade‑offs .

Hi Charles,

According to this diagram you provided:

Q. Is the customer’s proposed design technically feasible?

A: This design should be electrically feasible, but it will probably not satisfy the 802.3BT standard.

a. Since there is a 100-m CAT6A cable in between, the voltage drop on the cable might cause the input voltage on TPS23881 to drop below standard required value. The TPS23881 has a UVLO of 28 V, so it might turn-on and operate normally, but fail the compliance test.

b. The voltage on the 100-m CAT6A will be always on and causing large inrush current and voltage spikes when plug-in and unplug. 

These two might not affect the operation of the system electrically but will fail the 802.3BT compliance test.

Q: Can it support automatic detection and classification?

A: Yes, the detection and classification will still work.

For PoE adapter to supply the power, I would suggest to use TPS2372 rather then TPS2373 to eliminate the need for auxiliary supply for VC.

For the voltage drop on this 100-m CAT6a cable, it still needs to be measured to confirm the number.

Best regards,

Zhining

Hi Zhining,

Based on this design, will the detection resistor (R_detect) be correctly recognized during the PoE handshake?
We are concerned that because the line is passed directly through to the PD, the PSE (PoE adapter) may not correctly read the signature resistor. Since the resistor and the PD are on the same line, the effective resistance seen by the PSE might be altered, causing it to reject the device and withhold power.

Last reply you said :The operation of the system electrically may workable,and how should we design the part circuit?

For the Option 2 PoE pass‑through (daisy‑chain) implementation, could you share any available reference schematic or application note?

Is the flyback stage primarily intended to provide galvanic isolation?

Another idea: If we pass the PoE adapter's power signal directly to the PD device and wait for the PD device to receive the power, we could then convert the signal on this line to a Hi-V buck converter.

Is this approach feasible? We are concerned that the R-detect process might fail due to interference from the input capacitor of the buck converter, which could affect the timing.

Would it be possible to add some circuitry to mitigate this interference?

Would a dual-signature PD system be a better choice?

In this design, the R-detect issue would no longer be a concern because the system uses separate sets of pins (1236 and 4579).

Would you recommend adopting this approach, or are there other potential concerns we should be aware of?

Do you have any reference design circuits that we could use as a reference for this kind of PoE design?

Thanks for your help

Hi Charles,

Thanks for the following up.

Let me sort out the questions and details. I will get back to you in 2 business days.

Best regards,

Zhining

Hi Zhining,

Based on the above three architectures:

1. Dual-signature PD
2. PoE Daisy-Chaining
3. Customer's proposed idea

Which architecture do you think would be most suitable for this design in safety, simplicity, minimal component usage, and stability?

Safety and stability are the highest priorities. Valens has stressed the importance of being extremely cautious when designing this part.

Could you kindly provide reference designs and a list of recommended components for these architectures? This information is crucial as we need to estimate the required space to present to the customer.

Thank you.

Hi Charles,

Thank you for the patient and here are the updates from my side: 

Q1:

Based on this design, will the detection resistor (R_detect) be correctly recognized during the PoE handshake?

A: If the Hi-V converter is supplied by the TPS23881 per diagram above, the PSE PD detection will not work due to the input bus capacitance of the buck converter. The IEEE 802.3 has regulated the pairset capacitance to be smaller than 520 nF.

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Q2:

The operation of the system electrically may workable, and how should we design the part circuit?

A: According to this diagram. It will electrical work since the input of the buck is connected to the input side of TPS23881B. As long as TPS2372 finished handshake, the buck and TPS23881B will be powered up. For the design of this part circuit, TPS2372 and TPS23881B can be designed according to the reference design for each chip. But the key points are:

a. Please pay attention to the CAT6A cable length and measure the maximum voltage drop on the cable to make sure the input voltage of TPS23881B satisfy the min voltage requirement. If the voltage drop is too high, a boost converter will be needed.

b. Please pay attention to the application scenario on whether the CAT6A needs to be plugged and unplug after TPS2372 finishes the handshake. Once TPS2372 finished handshake, the PoE voltage will be applied. And the inrush current and voltage spike when plug and unplug CAT6A cable could cause some issue.

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Q3:

For the Option 2 PoE pass‑through (daisy‑chain) implementation, could you share any available reference schematic or application note?

A: For this daisy chain system, we have successful stories with existing EVM boards already. Many customers have implemented such structure in their system. The system diagram would be like this:

This system can be easily achieved with our existing EVM boards:

PSE: TPS23881B1EVM

PD: TPS2372EVM

Please check the schematic and application notes for these two EVMs as the reference.

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Q4:

Is the flyback stage primarily intended to provide galvanic isolation?

A: Yes. Per IEEE 802.3bt, the galvanic isolation is required.

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Q5:

Another idea: If we pass the PoE adapter's power signal directly to the PD device … Is this approach feasible?

A: For passive PoE adapter or PoE injector, this approach is feasible which means an always-on PoE voltage will be applied directly without handshake. But if it's a standard PSE device at PoE adapter, the handshake will fail and this approach is not feasible.

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Q6: Would a dual-signature PD system be a better choice?

A: The dual signature PD system per diagram here is feasible. However,

• The total Ethernet cable length needs to be < 100m, including the cable between left and right system + the cable between right system and PoE device.
• The left system will not have any power supplied from PoE. It has to rely on other power source (if any).

Based on these two reasons above, I would suggest that daisy chain structure is better since both systems will be supplied and middle CAT6A can be 100m regardless the distance between PoE device and right system.

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Q7:

Based on the above three architectures:

• Dual-signature PD
• PoE Daisy-Chaining
• Customer's proposed idea

Which architecture do you think would be most suitable for this design in safety, simplicity, minimal component usage, and stability?

Safety and stability are the highest priorities.

A:

Summarizing on all three approaches:

If you prioritize safety and stability, We would recommend the PoE daisy chain solution which we have successful stories already. It's fully 802.3 compliant, which means it's stable and reliable. You can refer to the system I mentioned above as a reference.

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Best regards,

Zhining

Hi Nick,

We are currently planning to evaluate and proceed with the design based on your recommended daisy chain architecture.

The current plan aligns with the previously provided block diagram, featuring a single output configuration.

Under these conditions, would the combination of TPS2372 and TPS23881B(8ch) be appropriate?
Alternatively, is there a better model that would be more suitable for the current design?

If we use Type-C VBUS 5V to power the VS6320, can we remove the yellow square?

If we change the Flyback converter to a Hi-V BUCK, will it cause R-detect issues?

thanks

Hi Charles,

Q: Under these conditions, would the combination of TPS2372 and TPS23881B(8ch) be appropriate?
Alternatively, is there a better model that would be more suitable for the current design?

A: Since you are looking at the single output configuration, I would suggest selecting the PD and PSE according to your power rating:

PSE: if the total power level from stage two and PoE load is higher than 30W, use TPS23881: if < 30W, use TPS23861

PD: if the PD required > 25.5W, use TPS2372, if the PD required < 25.5W，use TPS2378.

Q: If we use Type-C VBUS 5V to power the VS6320, can we remove the yellow square?

A: You can remove boost and flyback. But the LDO should be kept since the PSE will need a 3.3-V VDD.

Q: If we change the Flyback converter to a Hi-V BUCK, will it cause R-detect issues?

A: No. After TPS2372 finishes the handshake and the Hi-V buck converter will be powered on. 

Please let me know for any questions.

Best regards,

Zhining

Hi Zhining,

As shown in the following picture, I have labeled the power consumption.

The device-side board consumes less than 5W, and the PoE device will consume less than 40W.

Please provide suitable IC recommendations for these power consumption requirements.

thanks

Hi Charles,

According to the diagram you provided and the power rating, the recommended IC will be TPS2372 + TPS23881.

The TPS2372 will pass through 40W + 5W + converter loss on the device-side board.

The TPS23881 on the PC side board will provide the 40W + 5W + converter loss + 100-m cable loss < 90 W.

For the RT6365GQW here, you noted 60V, 2A. Please also clarify these numbers.

Best regards,

Zhining

Hi Zhining,

Do we need an MCU to control the status of the TPS23881, or can it configure itself automatically?

Please review the PoE system circuit and provide recommendations.

This is the system Block diagram

Host link:

https://drive.google.com/file/d/1mExkqxmlnL-p__55JG28awkYU4cveghb/view?usp=sharing

Device link:

drive.google.com/.../view

thanks

Hi Charles,

Thanks for updating the system diagram.

Q: Do we need an MCU to control the status of the TPS23881, or can it configure itself automatically?

A: For the PSE, you can use TPS23881B. It can run in autonomous mode without MCU. Link: TPS23881B data sheet, product information and support | TI.com

Q: Please review the PoE system circuit and provide recommendations.

A: Since you have total 45W + converter loss. I would suggest TPS2372-3 for PD and TPS23881B for PSE. 

Best regards,

Zhining

Hi Zhining,

Please help review the circuit of the Host and Device side PoE system.
Confirm the signal connection relationships and some definitions.

Host side

Device side 

thanks

Hi Charles, 

Here are some notes for the PSE side of the schematics you shared: 

1.TPS23881B does not require external resistors for DRAIN and SEN pins. These pins can be directly shorted to the FET.

2. Ensure that decoupling capacitors (near VDD and VPWR pins) have larger package size (either 0805 or 0603) to reduce capacitive degradation. 

3. Port fuse is needed between FET and RJ45 port. This fuse should be rated for minimum 60VDC. Please refer to TPS23881B datasheet for additional specifications. 

4. Seeing a 15.8kohm resistor connected to pin 52 - selecting 4-pair 60W power delivery. Assuming there is a typo for the naming of this pin (AUTO vs. AOUT).

Best,

Anagha

Hi Charles,

Please refer following comments for both Host and Device side PD.

1. Recommend to use 0805 res and cap for BS termination.

2. Recommend to put diode bridges before CMC and caps (PR12, PR36 going into KS-BD3 first then to KS-CM4 series)

3. Change this cap to 10 nF (total cap in 54V to Vss should not exceed 0.12 µF).

4. Leave AUTCLS pin open, you dont need auto class here.

Note: If you have a long cable between device side and host side. I would suggest you configure the Host side PD to Class 7 by changing R57 to 140 Ohm to assure enough margin for cable loss.

And please check Anagha's comments for PSE side circuit.

Best,

Zhining