BQ76972: PDSG/DSG FET Oscillating Re-enable after OCD3/2/1/SCD

Part Number: BQ76972
Other Parts Discussed in Thread: BQSTUDIO

Tool/software:

I am trying to test that the OCD1, 2, 3 and SCD functions correctly. Normally, our OCD thresholds will be in the hundreds of amps, but I am just trying to check basic functionality at lower currents. I've currently configured OCD2 to trigger at -48A. When I enable the load to pull 60A, I see OCD2 get triggered correctly in BQ-STUDIO, the DSG Vgs correctly is driven to 0V. It then is driven back on. OCD2 then triggers again, creating this oscillation. 

I see OCD2 Alert get set in BQ-STUDIO, not OCD2 Status. Then OCD2 Alert clears (unsure if that related - just an observation). 

I am just trying to have the DSG FET be disabled and stay off (including PDSG) after an OCD2. 

Interestingly enough, when I use the command ALL FETS OFF, the response is as expected - all FETs remain off. I have successfully used ALL FETS OFF for 720A.

Below are what I believe to be the relevant settings, and the oscilloscope captures. 

Red = DSG-VGS
Blue = PACK+

  • We are using the BQ76972 Battery Monitor on a 16s 48V pack with high side series FETs, predischarge FET and lowside shunts. We also are using a second BQ76972 as a battery protector for redundant control. There are two boards - the main BMS which has the MCU and BQ76972s, and then a second board that has the FETs and predischarge control. We are using 16 FETs in parallel for both CHARGE and DISCHARGE, so 32 FETs total. 
    BACKGROUND
    Everything has gone smoothly so far in bringup testing in terms of functionality, I have been communicating with the IC over I2C through the BQSTUDIO application. I can program the settings, but have yet to OTP the BQ76972. In terms of FET control, I have been using ALL-FETS-ON and ALL-FETS-OFF. While using the ALL-FETS-OFF command, I have successfully opened the FETs many times (>20 times) at up to 720A, no problem. We have adequate protection circuitry (so far). I am planning on using the autonomous mode for FET control, so if the BQ76972 senses a protection limit, it will command the FETs to open. We have included the recommended "local" fast gate turn off circuitry. 
    I'm trying to test the OCD1/2/3-SCD protections. To do this, I've mainly been only configuring the OCD settings (Enabling protections and alerts, setting Protections correct for timing/trip threshold). I set the OCD current trip thresholds very low to test quickly and safely, and to allow quick iteration while I get the kinks out before having their nominal threshold of ~1000A or greater.
    DESIRED BQ76972 RESPONSE
    When the BQ76972 senses an OC condition, I would like the FETs to open and STAY open (even if it's just the DSG FETs - I know the CHG FETs may not open in OCD1/2/3 scenarios, but all FETs should open in a SCD scenario). I do not want the BQ to auto retry, or use any of the latch settings. We have a 0.083mOhm shunt, and I have been able to get the BQ76972 to sense within 10% current accuracy, which is good enough for now for quick prototyping.

    TEST SETUP
    48V battery module connected to BMS BAT+/-, resistive cell divider that simulates cells (but off the same 48V battery module stack), load connected to PACK+/-. Oscilloscope probes on DSG Vgs, PACK+, BAT+. I have also configured the BQ to have a very high OCD recovery threshold
    HERE IS THE ISSUE I AM HAVING
    Currently, I have set OCD3 to -10A, and OCD2 to -48A. When I started testing for OCD3, I set the load to -20A. After the approximate expected delay time, I see the ALERT for OCD3 get set in BQSTUDIO, I have an oscilloscope probe on the Vgs of the DSG FETS. The DSG FETs correctly open, but then either the BQ commands them to "retry" to close, or there is some sort of noise that triggers the FETS to close again. The PDSG FET is re-enabled, and then sometimes it passes precharge, and the DSG FET is closed. The load is still running (and it itself has pretty large capacitance, so it can take a few seconds for the voltage to drop normally), and just continues to pull the CC load. The OCD3 ALERT is cleared automatically, and I don't visually see OCD3 FAULT getting set. It oscillates like this for a while. I will disable the load, and then the FETs DSG and CHG stay enabled, undamaged. I have normal control after that. 
    The same thing will happen if I disable OCD3, and then set the load to 60A to trigger OCD2. The same sort of response occurs with the DSG FETs. I've attached two oscilloscope photos of this issue on an OCD2 attempt. Ch1 (Yellow) = BAT+, Ch2 (Blue) = PACK+, Ch3 (Red) = DSG Vgs. 
    I have also attached what I believe are most/all of the relevant settings I'm configuring it with, but in screenshot and a relatively up-do configuration settings .gg.csv file. I have included relevant schematics as well.
    What I'm unsure about:
    • Why is OCD2/3 ALERT getting set, but OCD2/3 FAULT doesn't get set? (Unsure if this is just a BQSTUDIO sampling speed thing, and FAULT actually does get set, and then clears)
    • Why does this design seem to be totally fine when I use the ALL-FETS-OFF command? It also appears to be fine if I just command the DSG-PDSG-OFF. 
    This issue has occurred on multiple different boards, so it seems systemic. I believe it has also occurred during initial SCD testing (with trigger set to be ~280A). 
  •  We have great news - we were able to figure it out! It took some digging around E2E and inferring from other issues - we needed 0.1uF on both SRP/SRN to VSS. I was skeptical the device was under going a soft reset since we were only testing at 20A, but adding those capacitors fixed our issue! It does appear that soft resets were occurring - your intuition was correct. 

    When both pins reach a voltage too high relative to VSS (since they are meant to be tied or close to VSS) the device will undergo a hardware reset that doesn't clear data or RAM memory.

  • Hello Alec,

    I am glad your issue is fixed!

    Regards,

    Rohin Nair