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CSD17313Q2: Is thermal treatment necessary?

Shinichi Inoue
Guru 21616 points
Part Number: CSD17313Q2
Other Parts Discussed in Thread: TIDA-00890, PMP9491

Tool/software:

Dear Specialists,

My customer is considering CSD17313Q2 and has a question.

I would be grateful if you could advise.

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Regarding CSD17313Q2 datasheet, 

Recommended PCB layout is described datasheet P. 9,

However, there are no layout restrictions.

Are there any particular layout restrictions, thickness and thermal via ?

Especially is it needed thermal via for the 8-pin pad?

In our case, the application is USB3.0 Vbus(5V900mA) 

Could you provide PCB layout example?

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I appreciate your great help in advance/

Best regards,

Shinichi

  • 0
    TI__Mastermind 37970 points

    Hello Shinichi,

    Thanks for your interest in TI FETs. For the 2x2mm SON package, the customer should maximize the copper shape connecting to the drain pads. This is the main path to remove heat from the package. The size of the drain pad limits the number of thermal vias to probably 1 or 2 vias. The copper shape can be extended beyond package outline to accommodate additional thermal vias. There are many reference designs on TI.com that use this part including TIDA-00890 and PMP9491. You can download and view the gerber files using a free file viewer. Online Gerber Viewer at the link below allows you to load the zip file with the gerbers. Please review and let me know if you have any questions.

    https://www.gerber-viewer.com/

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    TI__Mastermind 37970 points

    Hi Shinichi,

    The link below is to a useful app note on QFN and SON PCB attachment.

    https://www.ti.com/lit/pdf/slua271

    Thanks,

    John