Tool/software:
Hi Team,
I am running some tests on TPSI31XXQ1EVM. I added some resistive loads across VDDH & VSSS as well as VDDM & VSSS to test load regulation of the IC. It came to my observation that if I decrease the value of resistance on VDDM, keeping the resistance on VDDH same, the voltage level of VDDH increases. Usually, the voltage level drops if we increase the load current, however my observation is different in this case.
Could you please let me know if I am missing something here? Also, if the observation is correct, what is the reason behind this?