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LP2951-N: Best practice for adding a resistor to increase the ESR of the output capacitors.

Andreas Kreindl
Prodigy 10 points
Part Number: LP2951-N

Tool/software:

Part: LP2951CMX/NOPB

What is the best practice for increasing the ESR of output capacitors in LDOs?

Often, multiple output capacitors are used in parallel because each chip that requires the LDO's output voltage also needs its own output capacitor. Therefore, adding a separate resistor for each output capacitor is not practical.

At the same time, the design should remain stable with future capacitors that may have significantly lower ESR than those used today.

For this reason, we want to add a resistor to ensure the LDO remains stable regardless of the specific output capacitors used.

What is the recommended best practice for adding this resistor?

In the schematic below, R4 increases the voltage drop under load. However, this is tolerable in most applications. Is this sufficient to ensure stability?

To improve this behaviour, it might be possible to place the resistor before the feedback pin. Would the solution using R3 still improve stability in this case?

Thank you for your help!





  • 0
    TI__Genius 13440 points

    Hi Andreas,

    If adding separate series resistance to the output capacitors, we recommend this be placed in series with the capacitor itself. As you note, placing this resistance at R4 can lead to degraded load regulation and load transient response.

    While resistance at R3 is likely a valid approach to resolving stability issues arising from ESR, we don't have any guidance on an analytical approach to this configuration at present. 

    Best Regards,

    Alex Davis

  • 0
    Prodigy 10 points

    Hi David,

    In our application, the load is relatively low (~14 mA), but we need the output voltage available at several points on the PCB.
    At each circuit where the voltage is used, we want to place a ceramic capacitor.
    Adding a series resistor to the capacitor is often not considered good practice—for example, in the supply of ICs (gate drivers, logic ICs, comparators, op-amps, etc.).

    Regarding R3: since we cannot confirm that R3 alone is sufficient, the most suitable position appears to be R4.
    With 0.2 Ω, the voltage drop is below 3 mV.

    Did we miss anything in these considerations?

    Thanks for your support.

  • 0 in reply to Andreas Kreindl
    TI__Genius 13440 points

    Hi Andreas,

    With a light load, placing the series resistor at R4 is acceptable.

    Best Regards,

    Alex Davis